4 Understanding Clocking Tradeoffs and What this Means to an ADC Performance

Now to the fun part of the application note. Here we discuss the many trades offs when trying to achieve good performance out of your high-speed converter design. We start with the source, which is the signal generator used as a sampling clock source in the lab. In this experiment, several signal generators were used. The signal generator's phase noise measurements can be found in Figure 4-1. These phase noise measurements represent a direct connection from the signal generator to a phase noise analyzer. All signal generators were configured with a 25MHz output signal and an +10dBm output power. Keep in mind that a signal generator can have specific upgrades or options that enhance the default configuration off the shelf.

Figure 4-1 Phase Noise Curves of Different Signal Sources at 25MHz and +10dBm Output Power Level

All the experiments used an ADC3683 evaluation board, or EVM, with three different 10MHz reference-locked signal generators, one providing the clock input, another the analog input, and the third one providing the data clock input required by the ADC3683, as shown in Figure 4-2. All of these inputs into the ADC3683 were filtered using bandpass filters to remove any other unwanted noise and spurious coming from the signal generators. The signal generator used for the data clock input was a R&S SGS100A. For the analog input, we used the highest performance signal generator available on the market as of September 2024, the R&S SMA100B. Both of these signal generators were kept constant throughout all experiments unless otherwise stated.

Figure 4-2 ADC Test Measurement Setup in the Lab

Figure 4-3 compares the converter’s AC performance, or SNR, across increasing analog input frequencies. Here, the ADC3683 is clocked at 25MSPS with the different signal generators used in Figure 4-1. For each source tested, the clock was held constant at +10dBm, and the analog input frequency was swept from 2MHz to 30MHz. At each frequency point, the analog signal source signal generator output power level was adjusted to -1dBFS before the SNR value (in dBFS) was measured. To keep the experiment consistent, the highest performance signal source was always used for the analog input source and was not changed. As seen in both Figure 3-1 (theoretical) and Figure 4-1 (practical), when the analog frequency increases, the SNR starts to roll off and worsens, or the SNR is jitter limited. This means that the jitter or phase noise of the ADC clock source and or clock signal chain begins to dominate the overall performance of the converter, leading to worse SNR from the ADC when operating the converter with of a noisier clock source. Each signal generator has a slightly different phase noise contribution as the analog input frequency gets higher, whereas, at lower frequencies, the phase noise has less of an impact.

Figure 4-3 ADC3683 SNR vs. Fin With Different Clocking Signal Source at 25MSPS and +10dBm When Operating the ADC With a -1dBFS Analog Input Signal

The clock slew rate is another key characteristic that affects the ADC performance. The sharper the slew rate of the clocking edge, the better the chance to reduce the clock jitter. Also, faster slew rates minimize the timing uncertainty of the sampling clock edge when the clock edge is moving through the ADC sampling threshold. Figure 4-4 demonstrates the effect of the sampling clock slew rate versus the performance of the ADC. As shown in the figure, when decreasing the amplitude level of the 25MSPS clock source from +10dBm to -15dBm, and maintaining a constant output power level for the analog input frequencies (of 5MHz, solid lines and 30MHz, dashed lines), the SNR begins to decrease as the clock signal source becomes -5dBm or smaller. Keep in mind, each ADC has a unique level of sensitivity and -5dBm doesn’t cover all ADC. -5dBm is only valid for this ADC test case and was used to demonstrate how sharper slew rates on the clock source lead to obtaining the best SNR from an ADC.

Figure 4-4 SNR vs. Sample Clock Amplitude (Slew Rate)