SBAA653 October   2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding the Difference Between Phase Noise and Jitter
  6. 3Understanding How Phase Noise or Jitter can Affect the ADC Performance
  7. 4Understanding Clocking Tradeoffs and What this Means to an ADC Performance
  8. 5Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance
  9. 6Summary
  10. 7References
  11.   Appendix A: Choosing a TI Clock Device Based on the TI High-Speed Converter Used

6 Summary

Providing a clean, high-slew rate clock source is paramount to maximizing the performance of any ADC, even though all the experimental cases shown in this paper were in the MSPS range. These fundamental points translate well when designing with GSPS ADC, or any high-speed ADC for that matter.

Understanding the difference between phase noise and jitter is also of utmost importance. Keep in mind, set the integration bandwidth upper limit to at least Fs, where 2×Fs is recommended, to capture the noise floor of the jitter contributed by the sampling clocking source. Another consideration is that the broadband noise floor is the largest noise contributor of the phase noise and/or jitter calculations. This quadrant of the phase noise curve has the largest impact on the ADC SNR performance.

Choosing a good, clean clock is paramount in achieving the ADC desired performance, especially since not all clock devices, oscillators, and signal sources are created equal. Filter the clock when appropriate to help knock down spurious and/or lower the broadband noise. However, there can be tradeoffs when using filters, since filters can decrease the clocking edge’s slew rate, and this too can affect an ADC performance.

Stay away from FPGA clocks, These clocks are simple to design and implement as FPGA clocks make a good, low cost alternative. However, if maximizing the ADC SNR performance is a top requirement in your design, these clocks do not have the performance required to achieve said ADC data sheet performance.

Lastly, choosing the correct clocking interface is also important. Differential signaling is key in choking out common mode noise and interference on your clocking signals. So, go with a LVPECL or CML style interfaces for best slew signal quality rather than LVDS or single ended LVCMOS clocking signal interfaces.

Overall, if achieving maximum SNR performance of your next ADC design is of utmost importance, then use all these considerations before for your next ADC clocking design shows pitfalls and gives you the jitters.