SBAA653 October   2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1205 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding the Difference Between Phase Noise and Jitter
  6. 3Understanding How Phase Noise or Jitter can Affect the ADC Performance
  7. 4Understanding Clocking Tradeoffs and What this Means to an ADC Performance
  8. 5Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance
  9. 6Summary
  10. 7References
  11.   Appendix A: Choosing a TI Clock Device Based on the TI High-Speed Converter Used

2 Understanding the Difference Between Phase Noise and Jitter

Good phase noise is paramount when maximizing the performance of any ADC. Understanding the sampling clock’s phase noise and the relationship to jitter is important when trying to achieve the desired converter’s rated performance.

Typically, a phase noise curve or plot is used to analyze the overall noise performance of a clock or clocking signal chain. Phase noise is the accumulation of any additive noise coming from the power supply or other noise contributors that influence the clock’s pure tone and lead to the signal deviating from the ideal. The signal wonders in phase, generating a phase noise curve around the analyzed signal tone. Jitter is then computed by integrating the signal tone’s phase noise curve over a specific frequency range, or an integration bandwidth. Figure 2-1 illustrates a phase noise curve with an integration bandwidth of 20Hz to 130MHz. The blue line is the phase noise curve being analyzed and the two red vertical lines represent the integration bandwidth limits.

Phase Noise Curve Using a Specific Integration Bandwidth to Obtain Jitter Figure 2-1 Phase Noise Curve Using a Specific Integration Bandwidth to Obtain Jitter

To calculate jitter, set the lower integration bandwidth limit to a value close to DC to consider the entire phase noise profile of the clock. In this application, we selected 20Hz. To obtain the upper integration limit, we recommended to use at least the ADC sampling frequency (Fs) and for an even better analysis, 2×Fs. For example, if the ADC was being sampled at 65MSPS, the integration bandwidth ranges from 20Hz to at least 65MHz (or up to 130MHz for a more detailed noise consideration). Many times, 2×Fs is more appropriate to understand the broadband noise contribution and make sure the sampling clock’s noise floor is reached.

After determining the integration bandwidth, jitter can be calculated from the phase noise curve. First, break each section into various quadrants broken up against a log scale, for example, 10kHz to 100kHz, 100kHz to 1MHz, and so on. Each quadrant is then integrated separately to determine the noise power. Each noise power is then added together to understand the total noise power under the curve. Finally, compute the RMS phase jitter in either radians or seconds from the total noise power. Figure 2-2 demonstrates how a phase noise curve is integrated to compute total jitter around a specified integration bandwidth using four quadrants.

Representation of Calculating Phase Noise to Jitter Using a Simpler Approach Figure 2-2 Representation of Calculating Phase Noise to Jitter Using a Simpler Approach