SBAA653 October   2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding the Difference Between Phase Noise and Jitter
  6. 3Understanding How Phase Noise or Jitter can Affect the ADC Performance
  7. 4Understanding Clocking Tradeoffs and What this Means to an ADC Performance
  8. 5Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance
  9. 6Summary
  10. 7References
  11.   Appendix A: Choosing a TI Clock Device Based on the TI High-Speed Converter Used

Abstract

There are many deliberations when creating designs with high-speed analog-to-digital converters, or ADC. Understanding the ADC sampling clocking is just one of these deliberations which is paramount to making sure your design requirements are met. There are several metrics that need to be understood about the ADC sampling clock that have a direct effect on the ADC performance (or signal-to-noise ratio, SNR) as discussed in the analog design journal article Clock jitter analyzed in the time domain Part 1, Part 2, and Part 3. However, from a practical stand point, what does that mean? In this application note, numerous experiments and tradeoffs are uncovered and proven on the bench to give better insight for your next high-speed ADC clock design.