SBAA653 October   2024 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Understanding the Difference Between Phase Noise and Jitter
  6. 3Understanding How Phase Noise or Jitter can Affect the ADC Performance
  7. 4Understanding Clocking Tradeoffs and What this Means to an ADC Performance
  8. 5Understanding How to Apply Clocking Tradeoffs to Achieve the Desired ADC Performance
  9. 6Summary
  10. 7References
  11.   Appendix A: Choosing a TI Clock Device Based on the TI High-Speed Converter Used

1 Introduction

In this application note, the tradeoffs of different clocking parameters are uncovered and proven on the bench. This demonstrates different common behaviors to avoid common pitfalls when designing your clock tree on your next high-speed converter design. Some relationships seen include the effect of the clock performance when increasing the analog input frequency, the clock slew rate's effect on the performance of the ADC, and so on.