SBAA653A October 2024 – April 2025 ADC3641 , ADC3642 , ADC3643 , ADC3661 , ADC3662 , ADC3663 , ADC3681 , ADC3682 , ADC3683 , LMK04368-EP , LMK04832 , LMK04832-SEP , LMK04832-SP , LMX1204 , LMX1205 , LMX1860-SEP , LMX1906-SP , LMX2571 , LMX2571-EP , LMX2572 , LMX2572LP , LMX2594 , LMX2595 , LMX2615-SP , LMX2694-EP , LMX2694-SEP , LMX2820
There are many deliberations when creating designs with high-speed analog-to-digital converters, or ADC. Understanding the ADC sampling clocking is just one of these deliberations which is paramount to making sure your design requirements are met. There are several metrics that need to be understood about the ADC sampling clock that have a direct effect on the ADC performance (or signal-to-noise ratio, SNR) as discussed in the analog design journal article Clock jitter analyzed in the time domain Part 1, Part 2, and Part 3. However, from a practical stand point, what does that mean? In this application note, numerous experiments and tradeoffs are uncovered and proven on the bench to give better insight for your next high-speed ADC clock design.
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In this application note, the tradeoffs of different clocking parameters are uncovered and proven on the bench. This demonstrates different common behaviors to avoid common pitfalls when designing your clock tree on your next high-speed converter design. Some relationships seen include the effect of the clock performance when increasing the analog input frequency, the clock slew rate's effect on the performance of the ADC, and so on.
Good phase noise is paramount when maximizing the performance of any ADC. Understanding the sampling clock’s phase noise and the relationship to jitter is important when trying to achieve the desired converter’s rated performance.
Typically, a phase noise curve or plot is used to analyze the overall noise performance of a clock or clocking signal chain. Phase noise is the accumulation of any additive noise coming from the power supply or other noise contributors that influence the clock’s pure tone and lead to the signal deviating from the ideal. The signal wonders in phase, generating a phase noise curve around the analyzed signal tone. Jitter is then computed by integrating the signal tone’s phase noise curve over a specific frequency range, or an integration bandwidth. Figure 2-1 illustrates a phase noise curve with an integration bandwidth of 20Hz to 130MHz. The blue line is the phase noise curve being analyzed and the two red vertical lines represent the integration bandwidth limits.
To calculate jitter, set the lower integration bandwidth limit to a value close to DC to consider the entire phase noise profile of the clock. In this application, we selected 20Hz. To obtain the upper integration limit, we recommended to use at least the ADC sampling frequency (Fs) and for an even better analysis, 2×Fs. For example, if the ADC was being sampled at 65MSPS, the integration bandwidth ranges from 20Hz to at least 65MHz (or up to 130MHz for a more detailed noise consideration). Many times, 2×Fs is more appropriate to understand the broadband noise contribution and make sure the sampling clock’s noise floor is reached.
After determining the integration bandwidth, jitter can be calculated from the phase noise curve. First, break each section into various quadrants broken up against a log scale, for example, 10kHz to 100kHz, 100kHz to 1MHz, and so on. Each quadrant is then integrated separately to determine the noise power. Each noise power is then added together to understand the total noise power under the curve. Finally, compute the RMS phase jitter in either radians or seconds from the total noise power. Figure 2-2 demonstrates how a phase noise curve is integrated to compute total jitter around a specified integration bandwidth using four quadrants.