SBAS502C December   2011  – April 2020 ADS1291 , ADS1292 , ADS1292R

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Block Diagram
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  EMI Filter
      2. 8.3.2  Input Multiplexer
        1. 8.3.2.1 Device Noise Measurements
        2. 8.3.2.2 Test Signals (TestP and TestN)
        3. 8.3.2.3 Auxiliary Differential Input (RESP_MODN/IN3N, RESP_MODN/IN3P)
        4. 8.3.2.4 Temperature Sensor (TEMPP, TEMPN)
        5. 8.3.2.5 Supply Measurements (MVDDP, MVDDN)
        6. 8.3.2.6 Lead-Off Excitation Signals (LoffP, LoffN)
        7. 8.3.2.7 Auxiliary Single-Ended Input
      3. 8.3.3  Analog Input
      4. 8.3.4  PGA Settings and Input Range
        1. 8.3.4.1 Input Common-Mode Range
        2. 8.3.4.2 Input Differential Dynamic Range
        3. 8.3.4.3 ADC ΔΣ Modulator
      5. 8.3.5  Digital Decimation Filter
        1. 8.3.5.1 Sinc Filter Stage (sinx / x)
      6. 8.3.6  Reference
      7. 8.3.7  Clock
      8. 8.3.8  Data Format
      9. 8.3.9  Multiple Device Configuration
        1. 8.3.9.1 Standard Mode
      10. 8.3.10 ECG-Specific Functions
        1. 8.3.10.1 Input Multiplexer (Rerouting the Right Leg Drive Signal)
          1. 8.3.10.1.1 Input Multiplexer (Measuring the Right Leg Drive Signal)
        2. 8.3.10.2 Lead-Off Detection
          1. 8.3.10.2.1 DC Lead-Off
          2. 8.3.10.2.2 AC Lead-Off
          3. 8.3.10.2.3 RLD Lead-Off
          4. 8.3.10.2.4 Right Leg Drive (RLD DC Bias Circuit)
            1. 8.3.10.2.4.1 RLD Configuration With Multiple Devices
        3. 8.3.10.3 PACE Detect
        4. 8.3.10.4 Respiration
          1. 8.3.10.4.1 Internal Respiration Circuitry With Internal Clock (ADS1292R)
          2. 8.3.10.4.2 Internal Respiration Circuitry With External Clock (ADS1292R)
      11. 8.3.11 Setting the Device for Basic Data Capture
        1. 8.3.11.1 Lead-Off
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Clock (SCLK)
        3. 8.5.1.3  Data Input (DIN)
        4. 8.5.1.4  Data Output (DOUT)
        5. 8.5.1.5  Data Retrieval
        6. 8.5.1.6  Data Ready (DRDY)
        7. 8.5.1.7  GPIO
        8. 8.5.1.8  Power-Down and Reset (PWDN/RESET)
        9. 8.5.1.9  START
        10. 8.5.1.10 Settling Time
        11. 8.5.1.11 Continuous Mode
        12. 8.5.1.12 Single-Shot Mode
      2. 8.5.2 SPI Command Definitions
        1. 8.5.2.1  WAKEUP: Exit STANDBY Mode
        2. 8.5.2.2  STANDBY: Enter STANDBY Mode
        3. 8.5.2.3  RESET: Reset Registers to Default Values
        4. 8.5.2.4  START: Start Conversions
        5. 8.5.2.5  STOP: Stop Conversions
        6. 8.5.2.6  OFFSETCAL: Channel Offset Calibration
        7. 8.5.2.7  RDATAC: Read Data Continuous
        8. 8.5.2.8  SDATAC: Stop Read Data Continuous
        9. 8.5.2.9  RDATA: Read Data
        10. 8.5.2.10 Sending Multi-Byte Commands
        11. 8.5.2.11 RREG: Read From Register
        12. 8.5.2.12 WREG: Write to Register
    6. 8.6 Register Maps
      1. 8.6.1 User Register Description
        1. 8.6.1.1  ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h)
          1. Table 17. ID: ID Control Register (Factory-Programmed, Read-Only) Field Descriptions
        2. 8.6.1.2  CONFIG1: Configuration Register 1 (address = 01h)
          1. Table 18. CONFIG1: Configuration Register 1 Field Descriptions
        3. 8.6.1.3  CONFIG2: Configuration Register 2 (address = 02h)
          1. Table 19. CONFIG2: Configuration Register 2 Field Descriptions
        4. 8.6.1.4  LOFF: Lead-Off Control Register (address = 03h)
          1. Table 20. LOFF: Lead-Off Control Register Field Descriptions
        5. 8.6.1.5  CH1SET: Channel 1 Settings (address = 04h)
          1. Table 21. CH1SET: Channel 1 Settings Field Descriptions
        6. 8.6.1.6  CH2SET: Channel 2 Settings (address = 05h)
          1. Table 22. CH2SET: Channel 2 Settings Field Descriptions
        7. 8.6.1.7  RLD_SENS: Right Leg Drive Sense Selection (address = 06h)
          1. Table 23. RLD_SENS: Right Leg Drive Sense Selection Field Descriptions
        8. 8.6.1.8  LOFF_SENS: Lead-Off Sense Selection (address = 07h)
          1. Table 24. LOFF_SENS: Lead-Off Sense Selection Field Descriptions
        9. 8.6.1.9  LOFF_STAT: Lead-Off Status (address = 08h)
          1. Table 25. LOFF_STAT: Lead-Off Status Field Descriptions
        10. 8.6.1.10 RESP1: Respiration Control Register 1 (address = 09h)
          1. Table 26. RESP1: Respiration Control Register 1 Field Descriptions
        11. 8.6.1.11 RESP2: Respiration Control Register 2 (address = 0Ah)
          1. Table 27. RESP2: Respiration Control Register 2 Field Descriptions
        12. 8.6.1.12 GPIO: General-Purpose I/O Register (address = 0Bh)
          1. Table 28. GPIO: General-Purpose I/O Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout
        1. 11.1.1.1 Power Supplies and Grounding
          1. 11.1.1.1.1 Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies
          2. 11.1.1.1.2 Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies
        2. 11.1.1.2 Shielding Analog Signal Paths
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from B Revision (September 2012) to C Revision

  • Added Device Information table, ESD Ratings table, title to page 1 figure, Recommended Operating Conditions table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Changed CMRR value from 105 dB to 120 dB in Features section Go
  • Changed Application section Go
  • Changed QFN to VQFN throughout document Go
  • Added thermal pad data to RDM pin out package drawing Go
  • Changed Pin Functions title from Pin Assignments, changed Terminal column header to Pin, and corrected format to show both package optionsGo
  • Changed function and description of RESP_MODN/IN3N and RESP_MODP/IN3P pins, changed function of RLDOUT pin from Analog input to Analog output, and added Thermal Pad row to Pin Assignments tableGo
  • Deleted Family and Ordering Information tableGo
  • Changed CMRR parameter values from –105 dB to 105 dB (minimum) and from –120 dB to 120 dB (typical) in Electrical Characteristics tableGo
  • Changed Noise Measurements section: deleted SNR equation, changed DYN RANGE and EFF RESOL column headers in section tablesGo
  • Added last sentence to Internal Respiration Circuitry with External Clock (ADS1292R) sectionGo
  • Changed denominator of equation 10 Go
  • Changed first paragraph of Data Output (DOUT) sectionGo
  • Changed RDATAC Usage figureGo
  • Changed RDATA Usage figureGo
  • Changed ADS1292R Application section to fulfill Typical Application sectionGo

Changes from A Revision (March 2012) to B Revision

  • Added QFN package to device graphicGo
  • Added QFN pin out drawingGo
  • Changed AVSS to DGND row in Absolute Maximum Ratings tableGo
  • Changed parameters of Supply Current (RLD Amplifier Turned Off) section in Electrical Characteristics tableGo
  • Changed description of bit 6 in LOFF_STATUS: Lead-Off Status registerGo

Changes from * Revision (December 2011) to A Revision

  • Changed device graphicGo
  • Changed device status from Mixed Status to Production DataGo
  • Changed second Features bulletGo
  • Updated Family and Ordering Information tableGo
  • Moved ADS1292R to production statusGo
  • Deleted footnote 2 from Family and Ordering Information tableGo
  • Changed values of AVDD to AVSS and DVDD to DGND rows in Absolute Maximum Ratings tableGo
  • Changed Operating temperature range parameter in Absolute Maximum Ratings tableGo
  • Changed DC Channel Performance, INL parameter test conditions in Electrical Characteristics tableGo
  • Changed AC Channel Performance, SNR and THD parameters test conditions in Electrical Characteristics tableGo
  • Added third Channel Performance, THD parameter row to Electrical Characteristics tableGo
  • Added Digital Filter section to Electrical Characteristics tableGo
  • Deleted Right Leg Drive Amplifier, Quiescent power consumption parameter test condition from Electrical Characteristics tableGo
  • Changed Respiration, Impedance measurement noise parameter test conditions in Electrical Characteristics tableGo
  • Changed Respiration, Maximum modulator current parameter in Electrical Characteristics tableGo
  • Changed Power-Supply Requirements, Digital supply parameter in Electrical Characteristics tableGo
  • Changed first IDVDD Supply Current, Normal mode parameter test conditions in Electrical Characteristics tableGo
  • Changed 3-V Power Dissipation, Quiescent power dissipation, per channel parameter typical specifications in Electrical Characteristics tableGo
  • Added CFILTER to Typical Characteristics conditionsGo
  • Updated Figure 5Go
  • Updated Figure 9 and Figure 12Go
  • Changed description of CHnSET setting in Supply Measurements (MVDDP, MVDDN) sectionGo
  • Changed second paragraph of PGA Settings and Input Range sectionGo
  • Changed description of PD_REFBUF bit in the Reference sectionGo
  • Updated second column title in Table 9Go
  • Updated Figure 33Go
  • Updated Figure 42Go
  • Added description of Figure 43, Figure 43, and Table 12 to Internal Respiration Circuitry with External Clock (ADS1292R) sectionGo
  • Updated description of DOUT and DRDY in RDATAC: Read Data Continuous sectionGo
  • Updated RLD_STAT in address 08h of Table 16Go
  • Changed description of bit 1 in CONFIG2: Configuration Register 2Go
  • Changed descriptions of bits[3:0] in CH2SET: Channel 2 SettingsGo
  • Updated Figure 70 and Figure 71Go
  • Updated Figure 73 and added footnote 1Go
  • Updated Figure 74 and added footnote 1Go