SBOA542 November   2022 TMP1826 , TMP1827

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Bus Reset and Response
    2. 1.2 Host Write, Device Read
    3. 1.3 Host Read, Device Write
  4. 2Interfacing TMP1826 With the Host MCU
    1. 2.1 Using GPIO as Host Interface
    2. 2.2 Software Driver for GPIO
    3. 2.3 Using UART as Host Interface
    4. 2.4 Software Driver for UART
    5. 2.5 Using SPI as Host Interface
    6. 2.6 Software Driver for SPI
  5. 3Summary
  6. 4References

1 Introduction

The single-wire interface for the TMP1826, does not have a reference clock. Therefore all communication is performed asynchronously with variable pulse widths to indicate different operations. Figure 1-1 shows that the bus consists of a single pullup resistor for all devices on the bus. The devices can be powered by the supply, where the VDD pin is connected to the same supply as the host MCU and pullup resistor or bus powered, where the VDD pin is connected to GND and the device derives power from the pullup resistor.

After power up, the external pullup resistor holds the line high which is referred to as the idle state. Almost all communication is initiated by the host by driving the data line low to generate a falling edge. Based on the duration of the low period, the device interprets the data bit as a reset request, logic '0' or logic '1'.

Figure 1-1 Simplified System Block Diagram