SFFS062 April 2021 INA302-Q1 , INA303-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the INA30x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to Supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the INA30x-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA30x-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- TA = -40°C to +125°C
- VS = 5 V
- VIN+ = 12 V
- REF = VS/2.
Table 4-2 Pin FMA for Device Pins Short-Circuited to
Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VS | 1 | Power supply shorted to ground | B |
| OUT | 2 | Output shorts to ground. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
| LIMIT1 | 3 | ALERT1 output is stuck low | B |
| REF | 4 | Comparators and analog output will be unpredictable. | B |
| GND | 5 | Normal Operation | D |
| LATCH1 | 6 | If intended connection is not GND, functionality will be affected. | D if LATCH1=GND by design; B otherwise |
| LATCH2 | 7 | If intended connection is not GND, functionality will be affected. | D if LATCH2=GND by design; B otherwise |
| NC | 8 | Normal Operation | D |
| LIMIT2 | 9 | ALERT2 output is stuck (low for INA302-q1; high for INA303-q1) | B |
| DELAY | 10 | ALERT2 may not trip | B |
| ALERT2 | 11 | ALERT2 output is stuck low | B |
| ALERT1 | 12 | ALERT1 output is stuck low | B |
| IN- | 13 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, normal operation | B for High side or D for low side |
| IN+ | 14 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, input pins are shorted. | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VS | 1 | No power supply to device. Device may be biased through inputs. Output will be close to GND. | B |
| OUT | 2 | Output can be left open, there is no effect on the IC.. | D |
| LIMIT1 | 3 | Comparator threshold is not defined. | B |
| REF | 4 | Comparators and analog output will be unpredictable. | B |
| GND | 5 | GND is floating. Output will be incorrect as it is no longer referenced to GND. | B |
| LATCH1 | 6 | Comparator1 mode is not defined. | B |
| LATCH2 | 7 | Comparator2 mode is not defined. | B |
| NC | 8 | Normal Operation | D |
| LIMIT2 | 9 | Comparator threshold is not defined. | B |
| DELAY | 10 | Delay time is not well defined | B |
| ALERT2 | 11 | Pin can be left open if not needed | D |
| ALERT1 | 12 | Pin can be left open if not needed | D |
| IN- | 13 | Differential input voltage is not well defined. | B |
| IN+ | 14 | Differential input voltage is not well defined. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| VS | 1 | OUT | Output shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
| OUT | 2 | LIMIT1 | Comparators and analog output will be unpredictable. | B |
| LIMIT1 | 3 | REF | Comparators and analog output will be unpredictable. | B |
| REF | 4 | GND | Comparators and analog output will be unpredictable. | B |
| GND | 5 | LATCH1 | LATCH1 short to GND. | D if LATCH1=GND by design; B otherwise |
| LATCH1 | 6 | LATCH2 | Normal Operation if LATCH1=LATCH2 by design, otherwise comparators operation is unpredictable. | D if LATCH1=LATCH2 by design; B otherwise |
| LATCH2 | 7 | NC | Normal Operation. | D |
| NC | 8 | LIMIT2 | Normal Operation. | D |
| LIMIT2 | 9 | DELAY | Neither the threshold or delay of comparator2 is well defined. Comparator2 will not function properly. | B |
| DELAY | 10 | ALERT2 | Delay of ALERT2 is unpredictable. | B |
| ALERT2 | 11 | ALERT1 | ALERT1 and ALERT2 are shorted and neither will function properly. | B |
| ALERT1 | 12 | IN- | In high-side configuration, device could be damaged. In low side configuration, ALERT1 pin is stuck to ground. | A for High side or B for low side |
| IN- | 13 | IN- | Input differential voltage=0V | C |
| IN+ | 14 | IN+ | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side or B for low side |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VS | 1 | Normal operation. | D |
| OUT | 2 | Output shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius. | B |
| LIMIT1 | 3 | ALERT1 is stuck high or unpredictable. | B |
| REF | 4 | Comparators and analog output will be unpredictable. | D if REF=VS by design; B otherwise |
| GND | 5 | Power supply shorted to GND | B |
| LATCH1 | 6 | Comparator1 in Latch mode. | D if LATCH1=VS by design; B otherwise |
| LATCH2 | 7 | Comparator2 in Latch mode. | D if LATCH2=VS by design; B otherwise |
| NC | 8 | Normal Operation. | D |
| LIMIT2 | 9 | ALERT2 output is stuck (high for INA302-q1; low for INA303-q1). | B |
| DELAY | 10 | Minimum Alert2 delay. | C |
| ALERT2 | 11 | ALERT2is stuck high. | B |
| ALERT1 | 12 | ALERT1is stuck high. | B |
| IN- | 13 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side or B for low side |
| IN+ | 14 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side or B for low side |