SLAA890A December 2019 – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133
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The ADC module of the MSP430FR4xx and MSP430FR2xx microcontrollers (MCUs) supports fast 10-bit or 12-bit analog-to-digital conversions. Depending on the device (see the device-specific data sheet for details), the module implements a 10-bit or 12-bit SAR core together with sample select control and a window comparator. The ADC IP described here is called the FR2xx/FR4xx ADC to distinguish it from the ADC12_B module that is used in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx devices.
FR2xx/FR4xx ADC features include:
In the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx MCUs, The ADC12_B module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, and up to 32 independent conversion-and-control buffers (ADC12MEM0 to ADC12MEM31). The conversion-and-control buffer allows up to 32 independent analog-to-digital converter (ADC) samples to be converted and stored without any CPU intervention.
ADC12_B supports 8 differential or 16 single-ended external inputs. ADC12_B has a dedicated memory control register for each input channel. This allows the user to set unique properties such as voltage reference input and provides a separate memory buffer for each channel of the ADC. For the ADC12_B on the FR59xx, 32 such memory control registers (ADC12MCTL0 to ADC12MCTL31) are provided. When a group of channels is sampled, the conversions results are stored sequentially and can be read after all the channels have completed sampling.
In the MSP430FR4xx and MSP430FR2xx MCUs, a single-ended external analog input is selected by the analog input multiplexer from 12 external and 4 internal analog signals. The 1.2-V VREF can be output to a device-specific external channel. The on-chip temperature sensor can be internally connected to channel A12. The 1.5-V VREF can be internally connected to channel A13.
In both the FR2xx/FR4xx ADC and the ADC12_B, 8-, 10-, or 12-bit resolution can be selected. In the FR2xx/FR4xx ADC module, the ADCCTL2.ADCRES bit field is used, and the default setting is 10 bit. In the ADC12_B module, the ADC12CTL2.ADC12RES bit field is used, and the default setting is 12 bit.
In MSP430FR4xx and MSP430FR2xx MCUs, the DMA is not supported. In MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx MCUs, the DMA is supported in the ADC12_B.
In MSP430FR4xx and MSP430FR2xx MCUs, the interrupt vector register ADCIV has six interrupt flag sources including three from the window comparator function. More ADC12_B interrupts are handled using the ADC12IV.
For the ADC clock source and sampling rate, MODOSC, ACLK, MCLK and SMCLK can be set as ADC clock. The conversion time can be calculated in (resolution bits + 2) × 1/fADCCLK. The sampling time can be set by ADCSHTx.ADCCTL0 to 4, 8, 16, and up to 1024 ADC clock cycles. The sampling time should be equal or larger than the minimum sampling time specified in MSP430FR4xx or MSP430FR2xx device-specific data sheet. This value is related to the equivalent internal and external resistance and capacitance, resolution, and voltage.