SLAA890A December   2019  – August 2021 MSP430FR2000 , MSP430FR2032 , MSP430FR2033 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111 , MSP430FR2153 , MSP430FR2155 , MSP430FR2310 , MSP430FR2311 , MSP430FR2353 , MSP430FR2355 , MSP430FR2422 , MSP430FR2433 , MSP430FR2475 , MSP430FR2476 , MSP430FR2512 , MSP430FR2522 , MSP430FR2532 , MSP430FR2533 , MSP430FR2632 , MSP430FR2633 , MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676 , MSP430FR4131 , MSP430FR4132 , MSP430FR4133

 

  1.   Trademarks
  2. 1Overview of the MSP430FR4xx and MSP430FR2xx ADC Module
  3. 2Comparison Between the FR2xx/FR4xx ADC and ADC12_B
    1. 2.1 Outline of ADC12_B
    2. 2.2 Outline of FR2xx/FR4xx ADC
    3. 2.3 FR2xx/FR4xx ADC Pin Selection and Board Design
    4. 2.4 Key Parameters Comparison
  4. 3Tailoring the ADC and Reference Voltages to Your Application
    1. 3.1 Reference Voltages
    2. 3.2 Internal and External Reference Voltage
    3. 3.3 Signal Resolution
    4. 3.4 Selecting the Right Sampling and Conversion Time to Achieve the Target Conversion Rate
    5. 3.5 Clock Selection
  5. 4Using the Window Comparator to Monitor a Signal Without CPU Intervention
  6. 5Calibration of VREF and the Internal Temperature Sensor to Improve Performance
  7. 6FR2xx/FR4xx ADC Example Code and Resources
  8. 7References
  9. 8Revision History

2.1 Outline of ADC12_B

In the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx MCUs, The ADC12_B module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, and up to 32 independent conversion-and-control buffers (ADC12MEM0 to ADC12MEM31). The conversion-and-control buffer allows up to 32 independent analog-to-digital converter (ADC) samples to be converted and stored without any CPU intervention.

ADC12_B supports 8 differential or 16 single-ended external inputs. ADC12_B has a dedicated memory control register for each input channel. This allows the user to set unique properties such as voltage reference input and provides a separate memory buffer for each channel of the ADC. For the ADC12_B on the FR59xx, 32 such memory control registers (ADC12MCTL0 to ADC12MCTL31) are provided. When a group of channels is sampled, the conversions results are stored sequentially and can be read after all the channels have completed sampling.