SLAAE75A November   2022  – March 2023 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1 MSPM0L Hardware Design Check List
  4. 2 Power Supplies in MSPM0L Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  5. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  6. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Clock Output (CLK_OUT)
    3. 4.3 Frequency Clock Counter (FCC)
  7. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  8. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  9. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  10. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High Speed GPIOs
    4. 8.4 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    5. 8.5 Communicate With 1.8-V Devices Without a Level Shifter
    6. 8.6 Unused Pins Connection
  11. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  12. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  13. 11References
  14. 12Revision History

8.5 Communicate With 1.8-V Devices Without a Level Shifter

The MSPM0L series devices use a 3.3-V logic level (excluding ODIO). To communicate with 1.8-V devices without an external level shifter device, #GUID-5B093D09-9DC9-4408-9B12-7F6341B2D9EA shows a suggested circuit for interfacing with a 1.8-V device.

GUID-E55A0257-E08A-4231-88B1-49BC9B9B1ACF-low.png Figure 8-2 Suggested Communication Circuit With 1.8-V Device

Two MOSFET are used in this circuit - check the VGS to ensure this MOSFET be able to fully turn on with a low RDS(on): for a 1.8-V device, use less than 1.8-V VGS MOSFET. However, do not use a too low VGS MOSFET, as this causes the MOSFET to turn on at a very small voltage (MCU logic judges it as 0), resulting in communication logic error.

U1 output and U2 input

  1. U1 output "1.8 V high", Q1 VGS around 0, thus Q1 turn off, U2 reads "3.3 V high" with R4.
  2. U1 output "low", Q1 VGS near 1.8 V, thus Q1 turn on, U2 reads "low".

U1 input and U2 output

  1. U2 output "3.3 V high", U1 keeps 1.8 V with R1, and Q1 turns off, thus U1 reads "1.8 V high".
  2. U2 output "low", U1 keeps 1.8 V with R1 at first, but the diode in the MOSFET pulls down U1 to 0.7 V (diode voltage drops), and then causes VGS to be greater than the turn-on voltage, Q1 turns on, and U1 reads "low".