SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA Channel Useburst Set (DMAUSEBURSTSET)
Each bit of the DMAUSEBURSTSET register represents the corresponding µDMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST.
If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n] bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the µDMA controller automatically clears the corresponding SET[n] bit, allowing the remaining items to transfer using single requests. In order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not support the burst request model.
Refer to Section 8.3.3 for more details about request types.
DMAUSEBURSTSET is shown in Figure 8-16 and described in Table 8-26.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SET[n] | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||