SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 8-18 lists the memory-mapped registers for the µDMA. All register offset addresses not listed in Table 8-18 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | DMASTAT | DMA Status | Section 8.6.1 |
0x4 | DMACFG | DMA Configuration | Section 8.6.2 |
0x8 | DMACTLBASE | DMA Channel Control Base Pointer | Section 8.6.3 |
0xC | DMAALTBASE | DMA Alternate Channel Control Base Pointer | Section 8.6.4 |
0x10 | DMAWAITSTAT | DMA Channel Wait-on-Request Status | Section 8.6.5 |
0x14 | DMASWREQ | DMA Channel Software Request | Section 8.6.6 |
0x18 | DMAUSEBURSTSET | DMA Channel Useburst Set | Section 8.6.7 |
0x1C | DMAUSEBURSTCLR | DMA Channel Useburst Clear | Section 8.6.8 |
0x20 | DMAREQMASKSET | DMA Channel Request Mask Set | Section 8.6.9 |
0x24 | DMAREQMASKCLR | DMA Channel Request Mask Clear | Section 8.6.10 |
0x28 | DMAENASET | DMA Channel Enable Set | Section 8.6.11 |
0x2C | DMAENACLR | DMA Channel Enable Clear | Section 8.6.12 |
0x30 | DMAALTSET | DMA Channel Primary Alternate Set | Section 8.6.13 |
0x34 | DMAALTCLR | DMA Channel Primary Alternate Clear | Section 8.6.14 |
0x38 | DMAPRIOSET | DMA Channel Priority Set | Section 8.6.15 |
0x3C | DMAPRIOCLR | DMA Channel Priority Clear | Section 8.6.16 |
0x4C | DMAERRCLR | DMA Bus Error Clear | Section 8.6.17 |
0x510 | DMACHMAP0 | DMA Channel Map Select 0 | Section 8.6.18 |
0x514 | DMACHMAP1 | DMA Channel Map Select 1 | Section 8.6.19 |
0x518 | DMACHMAP2 | DMA Channel Map Select 2 | Section 8.6.20 |
0x51C | DMACHMAP3 | DMA Channel Map Select 3 | Section 8.6.21 |
0xFD0 | DMAPeriphID4 | DMA Peripheral Identification 4 | Section 8.6.22 |
0xFE0 | DMAPeriphID0 | DMA Peripheral Identification 0 | Section 8.6.23 |
0xFE4 | DMAPeriphID1 | DMA Peripheral Identification 1 | Section 8.6.24 |
0xFE8 | DMAPeriphID2 | DMA Peripheral Identification 2 | Section 8.6.25 |
0xFEC | DMAPeriphID3 | DMA Peripheral Identification 3 | Section 8.6.26 |
0xFF0 | DMAPCellID0 | DMA PrimeCell Identification 0 | Section 8.6.27 |
0xFF4 | DMAPCellID1 | DMA PrimeCell Identification 1 | Section 8.6.28 |
0xFF8 | DMAPCellID2 | DMA PrimeCell Identification 2 | Section 8.6.29 |
0xFFC | DMAPCellID3 | DMA PrimeCell Identification 3 | Section 8.6.30 |
Complex bit access types are encoded to fit into small table cells. Table 8-19 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | 1C
W |
1 to clear
Write |
Reset or Default Value | ||
-n | Value after reset or the default value |