SLAU846B June   2023  – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN_G350x_G310x_G150x_G110x Registers
    6. 1.6 NONMAIN_G351x_G151x Registers
    7. 1.7 Factory Constants
      1. 1.7.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_G350x_G310x_G150x_G110x Registers
    7. 2.7 SYSCTL_G351x_G151x Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 DMA
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 MATHACL
    1. 6.1 Overview
    2. 6.2 Data Format
      1. 6.2.1 Unsigned 32-bit integers
      2. 6.2.2 Signed 32-bit integers
      3. 6.2.3 Unsigned 32-bit numbers
      4. 6.2.4 Signed 32-bit numbers
    3. 6.3 Basic Operation
    4. 6.4 Configuration Details with Examples
      1. 6.4.1 Sine and Cosine (SINCOS)
      2. 6.4.2 Arc Tangent (ATAN2)
      3. 6.4.3 Square Root (SQRT)
      4. 6.4.4 Division (DIV)
      5. 6.4.5 Multiplication
        1. 6.4.5.1 Multiply32 (MPY32)
        2. 6.4.5.2 Square32 (SQUARE32)
        3. 6.4.5.3 Multiply64 (MPY64)
        4. 6.4.5.4 Square64 (SQUARE64)
      6. 6.4.6 Multiply-Accumulate (MAC)
      7. 6.4.7 Square Accumulate (SAC)
    5. 6.5 MATHACL Registers
    6. 6.6 DMA Support for Accumulation Functions
  9. 7 NVM (Flash)
    1. 7.1 NVM Overview
      1. 7.1.1 Key Features
      2. 7.1.2 System Components
      3. 7.1.3 Terminology
    2. 7.2 Flash Memory Bank Organization
      1. 7.2.1 Banks
      2. 7.2.2 Flash Memory Regions
      3. 7.2.3 Addressing
        1. 7.2.3.1 Flash Memory Map
      4. 7.2.4 Memory Organization Examples
    3. 7.3 Flash Controller
      1. 7.3.1 Overview of Flash Controller Commands
      2. 7.3.2 NOOP Command
      3. 7.3.3 PROGRAM Command
        1. 7.3.3.1 Program Bit Masking Behavior
        2. 7.3.3.2 Programming Less Than One Flash Word
        3. 7.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 7.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 7.3.3.5 Executing a PROGRAM Operation
      4. 7.3.4 ERASE Command
        1. 7.3.4.1 Erase Sector Masking Behavior
        2. 7.3.4.2 Executing an ERASE Operation
      5. 7.3.5 READVERIFY Command
        1. 7.3.5.1 Executing a READVERIFY Operation
      6. 7.3.6 BLANKVERIFY Command
        1. 7.3.6.1 Executing a BLANKVERIFY Operation
      7. 7.3.7 Command Diagnostics
        1. 7.3.7.1 Command Status
        2. 7.3.7.2 Address Translation
        3. 7.3.7.3 Pulse Counts
      8. 7.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 7.3.9 FLASHCTL Events
        1. 7.3.9.1 CPU Interrupt Event Publisher
    4. 7.4 Write Protection
      1. 7.4.1 Write Protection Resolution
      2. 7.4.2 Static Write Protection
      3. 7.4.3 Dynamic Write Protection
        1. 7.4.3.1 Configuring Protection for the MAIN Region
        2. 7.4.3.2 Configuring Protection for the NONMAIN Region
    5. 7.5 Read Interface
      1. 7.5.1 Bank Address Swapping
      2. 7.5.2 ECC Error Handling
        1. 7.5.2.1 Single bit (correctable) errors
        2. 7.5.2.2 Dual bit (uncorrectable) errors
    6. 7.6 FLASHCTL_G350x_G310x_G150x_G110x Registers
    7. 7.7 FLASHCTL_G351x_G151x Registers
  10. 8 Events
    1. 8.1 Events Overview
      1. 8.1.1 Event Publisher
      2. 8.1.2 Event Subscriber
      3. 8.1.3 Event Fabric Routing
        1. 8.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 8.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 8.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 8.1.4 Event Routing Map
      5. 8.1.5 Event Propagation Latency
    2. 8.2 Events Operation
      1. 8.2.1 CPU Interrupt
      2. 8.2.2 DMA Trigger
      3. 8.2.3 Peripheral to Peripheral Event
      4. 8.2.4 Extended Module Description Register
      5. 8.2.5 Using Event Registers
        1. 8.2.5.1 Event Registers
        2. 8.2.5.2 Configuring Events
        3. 8.2.5.3 Responding to CPU Interrupts in Application Software
        4. 8.2.5.4 Hardware Event Handling
  11. 9 Low Frequency Subsystem (LFSS)
    1. 9.1 Overview
    2. 9.2 Clock System
    3. 9.3 LFSS Reset
    4. 9.4 Real Time Counter (RTC_x)
    5. 9.5 Independent Watchdog Timer (IWDT)
    6. 9.6 Scratchpad Memory
    7. 9.7 Lock Function of RTC and WDT
    8. 9.8 LFSS Registers
  12. 10IOMUX
    1. 10.1 IOMUX Overview
      1. 10.1.1 IO Types and Analog Sharing
    2. 10.2 IOMUX Operation
      1. 10.2.1 Peripheral Function (PF) Assignment
      2. 10.2.2 Logic High to Hi-Z Conversion
      3. 10.2.3 Logic Inversion
      4. 10.2.4 SHUTDOWN Mode Wakeup Logic
      5. 10.2.5 Pullup/Pulldown Resistors
      6. 10.2.6 Drive Strength Control
      7. 10.2.7 Hysteresis and Logic Level Control
    3. 10.3 IOMUX Registers
  13. 11GPIO
    1. 11.1 GPIO Overview
    2. 11.2 GPIO Operation
      1. 11.2.1 GPIO Ports
      2. 11.2.2 GPIO Read/Write Interface
      3. 11.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 11.2.4 GPIO Fast Wake
      5. 11.2.5 GPIO DMA Interface
      6. 11.2.6 Event Publishers and Subscribers
    3. 11.3 GPIO Registers
  14. 12ADC
    1. 12.1 ADC Overview
    2. 12.2 ADC Operation
      1. 12.2.1  ADC Core
      2. 12.2.2  Voltage Reference Options
      3. 12.2.3  Generic Resolution Modes
      4. 12.2.4  Hardware Averaging
      5. 12.2.5  ADC Clocking
      6. 12.2.6  Common ADC Use Cases
      7. 12.2.7  Power Down Behavior
      8. 12.2.8  Sampling Trigger Sources and Sampling Modes
        1. 12.2.8.1 AUTO Sampling Mode
        2. 12.2.8.2 MANUAL Sampling Mode
      9. 12.2.9  Sampling Period
      10. 12.2.10 Conversion Modes
      11. 12.2.11 Data Format
      12. 12.2.12 Advanced Features
        1. 12.2.12.1 Simultaneous Sampling
        2. 12.2.12.2 Window Comparator
        3. 12.2.12.3 DMA and FIFO Operation
        4. 12.2.12.4 Analog Peripheral Interconnection
      13. 12.2.13 Status Register
      14. 12.2.14 ADC Events
        1. 12.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 12.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 12.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 12.3 ADC12 Registers
  15. 13COMP
    1. 13.1 Comparator Overview
    2. 13.2 Comparator Operation
      1. 13.2.1  Comparator Configuration
      2. 13.2.2  Comparator Channels Selection
      3. 13.2.3  Comparator Output
      4. 13.2.4  Output Filter
      5. 13.2.5  Sampled Output Mode
      6. 13.2.6  Blanking Mode
      7. 13.2.7  Reference Voltage Generator
      8. 13.2.8  Window Comparator Mode
      9. 13.2.9  Comparator Hysteresis
      10. 13.2.10 Input SHORT Switch
      11. 13.2.11 Interrupt and Events Support
        1. 13.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 13.2.11.3 Generic Event Subscribers
    3. 13.3 COMP Registers
  16. 14OPA
    1. 14.1 OPA Overview
    2. 14.2 OPA Operation
      1. 14.2.1 Analog Core
      2. 14.2.2 Power Up Behavior
      3. 14.2.3 Inputs
      4. 14.2.4 Output
      5. 14.2.5 Clock Requirements
      6. 14.2.6 Chopping
      7. 14.2.7 OPA Amplifier Modes
        1. 14.2.7.1 General-Purpose Mode
        2. 14.2.7.2 Buffer Mode
        3. 14.2.7.3 OPA PGA Mode
          1. 14.2.7.3.1 Inverting PGA Mode
          2. 14.2.7.3.2 Non-inverting PGA Mode
        4. 14.2.7.4 Difference Amplifier Mode
        5. 14.2.7.5 Cascade Amplifier Mode
      8. 14.2.8 OPA Configuration Selection
      9. 14.2.9 Burnout Current Source
    3. 14.3 OA Registers
  17. 15GPAMP
    1. 15.1 GPAMP Overview
    2. 15.2 GPAMP Operation
      1. 15.2.1 Analog Core
      2. 15.2.2 Power Up Behavior
      3. 15.2.3 Inputs
      4. 15.2.4 Output
      5. 15.2.5 GPAMP Amplifier Modes
        1. 15.2.5.1 General-Purpose Mode
        2. 15.2.5.2 ADC Buffer Mode
        3. 15.2.5.3 Unity Gain Mode
      6. 15.2.6 Chopping
    3. 15.3 GPAMP Registers
  18. 16DAC
    1. 16.1 DAC Introduction
    2. 16.2 DAC Operation
      1. 16.2.1  DAC Core
      2. 16.2.2  DAC Output
      3. 16.2.3  DAC Voltage Reference
      4. 16.2.4  DAC Output Buffers
      5. 16.2.5  DAC Data Formats
      6. 16.2.6  Sample Time Generator
      7. 16.2.7  DAC FIFO Structure
        1. 16.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 16.2.8  DAC Operation With DMA Controller
        1. 16.2.8.1 DMA Trigger Interface
        2. 16.2.8.2 DMA Status Interface
        3. 16.2.8.3 DMA Trigger Generation Scheme
      9. 16.2.9  DAC Operation With CPU
        1. 16.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 16.2.10 Data Register Format
      11. 16.2.11 DAC Output Amplifier Offset Calibration
      12. 16.2.12 Interrupt and Event Support
        1. 16.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.12.3 DMA Trigger Event Publisher
        4. 16.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 16.3 DAC12 Registers
  19. 17VREF
    1. 17.1 VREF Overview
    2. 17.2 VREF Operation
      1. 17.2.1 Internal Reference Generation
      2. 17.2.2 External Reference Input
      3. 17.2.3 Analog Peripheral Interface
    3. 17.3 VREF Registers
  20. 18UART
    1. 18.1 UART Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
    2. 18.2 UART Operation
      1. 18.2.1 Clock Control
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture and Protocol
        1. 18.2.3.1  Transmit Receive Logic
        2. 18.2.3.2  Bit Sampling
        3. 18.2.3.3  Majority Voting Feature
        4. 18.2.3.4  Baud Rate Generation
        5. 18.2.3.5  Data Transmission
        6. 18.2.3.6  Error and Status
        7. 18.2.3.7  Local Interconnect Network (LIN) Support
          1. 18.2.3.7.1 LIN Responder Transmission Delay
        8. 18.2.3.8  Flow Control
        9. 18.2.3.9  Idle-Line Multiprocessor
        10. 18.2.3.10 9-Bit UART Mode
        11. 18.2.3.11 RS485 Support
        12. 18.2.3.12 DALI Protocol
        13. 18.2.3.13 Manchester Encoding and Decoding
        14. 18.2.3.14 IrDA Encoding and Decoding
        15. 18.2.3.15 ISO7816 Smart Card Support
        16. 18.2.3.16 Address Detection
        17. 18.2.3.17 FIFO Operation
        18. 18.2.3.18 Loopback Operation
        19. 18.2.3.19 Glitch Suppression
      4. 18.2.4 Low Power Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 18.2.8 Emulation Modes
    3. 18.3 UART Registers
  21. 19SPI
    1. 19.1 SPI Overview
      1. 19.1.1 Purpose of the Peripheral
      2. 19.1.2 Features
      3. 19.1.3 Functional Block Diagram
      4. 19.1.4 External Connections and Signal Descriptions
    2. 19.2 SPI Operation
      1. 19.2.1 Clock Control
      2. 19.2.2 General Architecture
        1. 19.2.2.1 Chip Select and Command Handling
          1. 19.2.2.1.1 Chip Select Control
          2. 19.2.2.1.2 Command Data Control
        2. 19.2.2.2 Data Format
        3. 19.2.2.3 Delayed data sampling
        4. 19.2.2.4 Clock Generation
        5. 19.2.2.5 FIFO Operation
        6. 19.2.2.6 Loopback mode
        7. 19.2.2.7 DMA Operation
        8. 19.2.2.8 Repeat Transfer mode
        9. 19.2.2.9 Low Power Mode
      3. 19.2.3 Protocol Descriptions
        1. 19.2.3.1 Motorola SPI Frame Format
        2. 19.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 19.2.4 Reset Considerations
      5. 19.2.5 Initialization
      6. 19.2.6 Interrupt and Events Support
        1. 19.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 19.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 19.2.7 Emulation Modes
    3. 19.3 SPI Registers
  22. 20I2C
    1. 20.1 I2C Overview
      1. 20.1.1 Purpose of the Peripheral
      2. 20.1.2 Features
      3. 20.1.3 Functional Block Diagram
      4. 20.1.4 Environment and External Connections
    2. 20.2 I2C Operation
      1. 20.2.1 Clock Control
        1. 20.2.1.1 Clock Select and I2C Speed
        2. 20.2.1.2 Clock Startup
      2. 20.2.2 Signal Descriptions
      3. 20.2.3 General Architecture
        1. 20.2.3.1  I2C Bus Functional Overview
        2. 20.2.3.2  START and STOP Conditions
        3. 20.2.3.3  Data Format with 7-Bit Address
        4. 20.2.3.4  Acknowledge
        5. 20.2.3.5  Repeated Start
        6. 20.2.3.6  SCL Clock Low Timeout
        7. 20.2.3.7  Clock Stretching
        8. 20.2.3.8  Dual Address
        9. 20.2.3.9  Arbitration
        10. 20.2.3.10 Multiple Controller Mode
        11. 20.2.3.11 Glitch Suppression
        12. 20.2.3.12 FIFO operation
          1. 20.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 20.2.3.13 Loopback mode
        14. 20.2.3.14 Burst Mode
        15. 20.2.3.15 DMA Operation
        16. 20.2.3.16 Low-Power Operation
      4. 20.2.4 Protocol Descriptions
        1. 20.2.4.1 I2C Controller Mode
          1. 20.2.4.1.1 Controller Configuration
          2. 20.2.4.1.2 Controller Mode Operation
          3. 20.2.4.1.3 Read On TX Empty
        2. 20.2.4.2 I2C Target Mode
          1. 20.2.4.2.1 Target Mode Operation
      5. 20.2.5 Reset Considerations
      6. 20.2.6 Initialization
      7. 20.2.7 Interrupt and Events Support
        1. 20.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 20.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 20.2.8 Emulation Modes
    3. 20.3 I2C Registers
  23. 21CAN-FD
    1. 21.1 MCAN Overview
      1. 21.1.1 MCAN Features
    2. 21.2 MCAN Environment
    3. 21.3 CAN Network Basics
    4. 21.4 MCAN Functional Description
      1. 21.4.1  Clock Set up
      2. 21.4.2  Module Clocking Requirements
      3. 21.4.3  Interrupt Requests
      4. 21.4.4  Operating Modes
        1. 21.4.4.1 Normal Operation
        2. 21.4.4.2 CAN Classic
        3. 21.4.4.3 CAN FD Operation
      5. 21.4.5  Software Initialization
      6. 21.4.6  Transmitter Delay Compensation
        1. 21.4.6.1 Description
        2. 21.4.6.2 Transmitter Delay Compensation Measurement
      7. 21.4.7  Restricted Operation Mode
      8. 21.4.8  Bus Monitoring Mode
      9. 21.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 21.4.9.1 Frame Transmission in DAR Mode
      10. 21.4.10 Clock Stop Mode
        1. 21.4.10.1 Suspend Mode
        2. 21.4.10.2 Wakeup Request
      11. 21.4.11 Test Modes
        1. 21.4.11.1 External Loop Back Mode
        2. 21.4.11.2 Internal Loop Back Mode
      12. 21.4.12 Timestamp Generation
        1. 21.4.12.1 External Timestamp Counter
      13. 21.4.13 Timeout Counter
      14. 21.4.14 Safety
        1. 21.4.14.1 ECC Wrapper
        2. 21.4.14.2 ECC Aggregator
          1. 21.4.14.2.1 ECC Aggregator Overview
          2. 21.4.14.2.2 ECC Aggregator Registers
        3. 21.4.14.3 Reads to ECC Control and Status Registers
        4. 21.4.14.4 ECC Interrupts
      15. 21.4.15 Tx Handling
        1. 21.4.15.1 Transmit Pause
        2. 21.4.15.2 Dedicated Tx Buffers
        3. 21.4.15.3 Tx FIFO
        4. 21.4.15.4 Tx Queue
        5. 21.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 21.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 21.4.15.7 Transmit Cancellation
        8. 21.4.15.8 Tx Event Handling
        9. 21.4.15.9 FIFO Acknowledge Handling
      16. 21.4.16 Rx Handling
        1. 21.4.16.1 Acceptance Filtering
          1. 21.4.16.1.1 Range Filter
          2. 21.4.16.1.2 Filter for Specific IDs
          3. 21.4.16.1.3 Classic Bit Mask Filter
          4. 21.4.16.1.4 Standard Message ID Filtering
          5. 21.4.16.1.5 Extended Message ID Filtering
      17. 21.4.17 Rx FIFOs
        1. 21.4.17.1 Rx FIFO Blocking Mode
        2. 21.4.17.2 Rx FIFO Overwrite Mode
      18. 21.4.18 Dedicated Rx Buffers
        1. 21.4.18.1 Rx Buffer Handling
      19. 21.4.19 Message RAM
        1. 21.4.19.1 Message RAM Configuration
        2. 21.4.19.2 Rx Buffer and FIFO Element
        3. 21.4.19.3 Tx Buffer Element
        4. 21.4.19.4 Tx Event FIFO Element
        5. 21.4.19.5 Standard Message ID Filter Element
        6. 21.4.19.6 Extended Message ID Filter Element
    5. 21.5 MCAN Integration
    6. 21.6 Interrupt and Event Support
      1. 21.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 21.7 MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRCP0 Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24AESADV
    1. 24.1 AESADV Overview
      1. 24.1.1 AESADV Performance
    2. 24.2 AESADV Operation
      1. 24.2.1 Loading the Key
      2. 24.2.2 Writing Input Data
      3. 24.2.3 Reading Output Data
      4. 24.2.4 Operation Descriptions
        1. 24.2.4.1 Single Block Operation
        2. 24.2.4.2 Electronic Codebook (ECB) Mode
          1. 24.2.4.2.1 ECB Encryption
          2. 24.2.4.2.2 ECB Decryption
        3. 24.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 24.2.4.3.1 CBC Encryption
          2. 24.2.4.3.2 CBC Decryption
        4. 24.2.4.4 Output Feedback (OFB) Mode
          1. 24.2.4.4.1 OFB Encryption
          2. 24.2.4.4.2 OFB Decryption
        5. 24.2.4.5 Cipher Feedback (CFB) Mode
          1. 24.2.4.5.1 CFB Encryption
          2. 24.2.4.5.2 CFB Decryption
        6. 24.2.4.6 Counter (CTR) Mode
          1. 24.2.4.6.1 CTR Encryption
          2. 24.2.4.6.2 CTR Decryption
        7. 24.2.4.7 Galois Counter (GCM) Mode
          1. 24.2.4.7.1 GHASH Operation
          2. 24.2.4.7.2 GCM Operating Modes
            1. 24.2.4.7.2.1 Autonomous GCM Operation
              1. 24.2.4.7.2.1.1 GMAC
            2. 24.2.4.7.2.2 GCM With Pre-Calculations
            3. 24.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 24.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 24.2.4.8.1 CCM Operation
      5. 24.2.5 AES Events
        1. 24.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 24.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 24.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 24.3 AESADV Registers
  27. 25Keystore
    1. 25.1 Overview
    2. 25.2 Detailed Description
    3. 25.3 KEYSTORECTL Registers
  28. 26TRNG
    1. 26.1 TRNG Overview
    2. 26.2 TRNG Operation
      1. 26.2.1 TRNG Generation Data Path
      2. 26.2.2 Clock Configuration and Output Rate
      3. 26.2.3 Behavior in Low Power Modes
      4. 26.2.4 Health Tests
        1. 26.2.4.1 Digital Block Startup Self-Test
        2. 26.2.4.2 Analog Block Startup Self-Test
        3. 26.2.4.3 Runtime Health Test
          1. 26.2.4.3.1 Repetition Count Test
          2. 26.2.4.3.2 Adaptive Proportion Test
          3. 26.2.4.3.3 Handling Runtime Health Test Failures
      5. 26.2.5 Configuration
        1. 26.2.5.1 TRNG State Machine
          1. 26.2.5.1.1 Changing TRNG States
        2. 26.2.5.2 Using the TRNG
        3. 26.2.5.3 TRNG Events
          1. 26.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 26.3 TRNG Registers
  29. 27Timers (TIMx)
    1. 27.1 TIMx Overview
      1. 27.1.1 TIMG Overview
        1. 27.1.1.1 TIMG Features
        2. 27.1.1.2 Functional Block Diagram
      2. 27.1.2 TIMA Overview
        1. 27.1.2.1 TIMA Features
        2. 27.1.2.2 Functional Block Diagram
      3. 27.1.3 TIMx Instance Configuration
    2. 27.2 TIMx Operation
      1. 27.2.1  Timer Counter
        1. 27.2.1.1 Clock Source Select and Prescaler
          1. 27.2.1.1.1 Internal Clock and Prescaler
          2. 27.2.1.1.2 External Signal Trigger
        2. 27.2.1.2 Repeat Counter (TIMA only)
      2. 27.2.2  Counting Mode Control
        1. 27.2.2.1 One-shot and Periodic Modes
        2. 27.2.2.2 Down Counting Mode
        3. 27.2.2.3 Up/Down Counting Mode
        4. 27.2.2.4 Up Counting Mode
        5. 27.2.2.5 Phase Load (TIMA only)
      3. 27.2.3  Capture/Compare Module
        1. 27.2.3.1 Capture Mode
          1. 27.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 27.2.3.1.1.1 CCP Input Edge Synchronization
            2. 27.2.3.1.1.2 CCP Input Pulse Conditions
            3. 27.2.3.1.1.3 Counter Control Operation
            4. 27.2.3.1.1.4 CCP Input Filtering
            5. 27.2.3.1.1.5 Input Selection
          2. 27.2.3.1.2 Use Cases
            1. 27.2.3.1.2.1 Edge Time Capture
            2. 27.2.3.1.2.2 Period Capture
            3. 27.2.3.1.2.3 Pulse Width Capture
            4. 27.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 27.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 27.2.3.1.3.1 QEI With 2-Signal
            2. 27.2.3.1.3.2 QEI With Index Input
            3. 27.2.3.1.3.3 QEI Error Detection
          4. 27.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 27.2.3.2 Compare Mode
          1. 27.2.3.2.1 Edge Count
      4. 27.2.4  Shadow Load and Shadow Compare
        1. 27.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 27.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 27.2.5  Output Generator
        1. 27.2.5.1 Configuration
        2. 27.2.5.2 Use Cases
          1. 27.2.5.2.1 Edge-Aligned PWM
          2. 27.2.5.2.2 Center-Aligned PWM
          3. 27.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 27.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 27.2.5.3 Forced Output
      6. 27.2.6  Fault Handler (TIMA only)
        1. 27.2.6.1 Fault Input Conditioning
        2. 27.2.6.2 Fault Input Sources
        3. 27.2.6.3 Counter Behavior With Fault Conditions
        4. 27.2.6.4 Output Behavior With Fault Conditions
      7. 27.2.7  Synchronization With Cross Trigger
        1. 27.2.7.1 Main Timer Cross Trigger Configuration
        2. 27.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 27.2.8  Low Power Operation
      9. 27.2.9  Interrupt and Event Support
        1. 27.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 27.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 27.2.10 Debug Handler (TIMA Only)
    3. 27.3 TIMx Registers
  30. 28RTC
    1. 28.1 Overview
      1. 28.1.1 RTC Instances
    2. 28.2 Basic Operation
    3. 28.3 Configuration
      1. 28.3.1  Clocking
      2. 28.3.2  Reading and Writing to RTC Peripheral Registers
      3. 28.3.3  Binary vs. BCD
      4. 28.3.4  Leap Year Handling
      5. 28.3.5  Calendar Alarm Configuration
      6. 28.3.6  Interval Alarm Configuration
      7. 28.3.7  Periodic Alarm Configuration
      8. 28.3.8  Calibration
        1. 28.3.8.1 Crystal Offset Error
          1. 28.3.8.1.1 Offset Error Correction Mechanism
        2. 28.3.8.2 Crystal Temperature Error
          1. 28.3.8.2.1 Temperature Drift Correction Mechanism
      9. 28.3.9  RTC Prescaler Extension
      10. 28.3.10 RTC Timestamp Capture
      11. 28.3.11 RTC Events
        1. 28.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 28.4 RTC Registers
  31. 29IWDT
    1. 29.1 834
    2. 29.2 IWDT Clock Configuration
    3. 29.3 IWDT Period Selection
    4. 29.4 Debug Behavior of the IWDT
    5. 29.5 IWDT Registers
  32. 30WWDT
    1. 30.1 WWDT Overview
      1. 30.1.1 Watchdog Mode
      2. 30.1.2 Interval Timer Mode
    2. 30.2 WWDT Operation
      1. 30.2.1 Mode Selection
      2. 30.2.2 Clock Configuration
      3. 30.2.3 Low-Power Mode Behavior
      4. 30.2.4 Debug Behavior
      5. 30.2.5 WWDT Events
        1. 30.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 30.3 WWDT Registers
  33. 31Debug
    1. 31.1 DEBUGSS Overview
      1. 31.1.1 Debug Interconnect
      2. 31.1.2 Physical Interface
      3. 31.1.3 Debug Access Ports
    2. 31.2 DEBUGSS Operation
      1. 31.2.1 Debug Features
        1. 31.2.1.1 Processor Debug
          1. 31.2.1.1.1 Breakpoint Unit (BPU)
          2. 31.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
          3. 31.2.1.1.3 Processor Trace (MTB)
        2. 31.2.1.2 Peripheral Debug
        3. 31.2.1.3 EnergyTrace Technology
      2. 31.2.2 Behavior in Low Power Modes
      3. 31.2.3 Restricting Debug Access
      4. 31.2.4 Mailbox (DSSM)
        1. 31.2.4.1 DSSM Events
          1. 31.2.4.1.1 CPU Interrupt Event (CPU_INT)
    3. 31.3 DEBUGSS Registers
  34. 32Revision History

2.3.2.1 MCLK (Main Clock) Tree

The MCLK is the main system clock and the root point of synchronization for all synchronized clocks (MCLK, CPUCLK, ULPCLK, MFCLK, and LFCLK). It is typically the highest speed clock in the system and supports operation up to 80MHz across the full temperature range of the device. The MCLK tree is the root source for the CPUCLK (in RUN mode), the PD1 high speed peripheral bus clock (in RUN and SLEEP modes), and the ULPCLK low power bus clock (in RUN, SLEEP, STOP, and STANDBY modes). In addition, the 4MHz MFCLK and 32kHz LFCLK outputs are synchronized to MCLK.

The MCLK output to PD1 peripherals is enabled in RUN and SLEEP modes, and disabled in all other power modes. While the MCLK output to PD1 is disabled in STOP and STANDBY modes, the MCLK tree is still running to source ULPCLK and to provide synchronization for MFCLK and LFCLK.

The MCLK source is selected with a glitch free clock mux and can be changed dynamically at runtime by user software. It can also be changed automatically by hardware when entering STOP and STANDBY modes or during an asynchronous fast clock request.

The available sources for MCLK include:

  • HSCLK (high-speed clock) at up to 80MHz which can be sourced by:
    • SYSPLLCLK0 or SYSPLLCLK2X (used to reach the max MCLK speed of 80MHz)
    • HFCLK for applications where the main clock needs to be as accurate as possible
  • SYSOSC at 4, 16, 24, or 32MHz (the default clock source after reset)
  • SYSOSC at 4MHz with MDIV divider (for applications where the peripheral bus and CPU run between 250kHz and 4MHz)
  • LFCLK at 32kHz for applications where the entire system, including the CPU, runs at 32kHz with low peak operating current

NOTE: Set SYSPLLCLK0 or SYSPLLCLK2X as the source of HSCLK before setting HSCLK as the clock source of MCLK, otherwise the device can be in an unpredictable state.

Using MCLK in RUN and SLEEP Mode

After boot, MCLK is sourced from SYSOSC by default. The decision of which oscillator to use to source MCLK is important because MCLK sets both the CPUCLK frequency and the bus clock frequency for PD1 peripherals. As a result, the accuracy and the clock speed of the oscillator selected for MCLK must be appropriate not only for the operation of the CPU but also for the operation of the PD1 peripherals that use the bus clock as their functional clock.

The clock source and frequency selection decisions made for MCLK also affect ULPCLK in RUN and SLEEP modes. See the ULPCLK section for more information on how MCLK and ULPCLK are related in RUN and SLEEP mode.

Using MCLK in STOP and STANDBY Mode

In STOP and STANDBY modes, the MCLK output to PD1 peripherals is disabled, but the ULPCLK, which is the bus clock for PD0 peripherals, is still active in STOP and optionally active in STANDBY. See the ULPCLK section for more information on how the MCLK source and ULPCLK are related in STOP and STANDBY mode.

MCLK Source Selection

Application software can change the MCLK source from SYSOSC to the SYSPLL or to the HFCLK (which is either HFXT or HFCLK_IN) by configuring the MCLKCFG.USEHSCLK and HSCLKCFG.HSCLKSEL register bits appropriately in SYSCTL. It is also possible to select LFCLK as the MCLK source in all modes by setting MCLKCFG.USELFCLK, giving the low peak current consumption with the CPU and PD1 peripherals operational. The following table gives the proper register bit configurations for selecting different clocks for MCLK in RUN and SLEEP modes.

Table 2-7 MSPM0Gxx MCLK Source Selection in RUN and SLEEP Mode
Desired Source MCLKCFG.USEHSCLK MCLKCFG.USELFCLK HSCLKCFG.HSCLKSEL SYSPLLCFG0.MCLK2XVCO
SYSOSC 0 0 Don't care Don't care
SYSPLLCLK0 1 0 0 0
SYSPLLCLK2X 1 0 0 1
HFCLK 1 0 1 Don't care
LFCLK 0 1 Don't care Don't care

To switch MCLK from SYSOSC to LFCLK in RUN mode:

  1. If any high speed oscillators (SYSPLL, HFXT, HFCLK_IN) are enabled, disable them before proceeding
  2. Verify that MCLK is sourced from SYSOSC (CLKSTATUS.CURMCLKSEL is cleared)
  3. If SYSOSC is not running at base frequency, and SYSOSC is to be left enabled when switching MCLK to LFCLK, set SYSOSC to base frequency before proceeding
  4. Set MCLKCFG.USELFCLK to switch MCLK to LFCLK and leave SYSOSC enabled, or set SYSOSCCFG.DISABLE to switch MCLK to LFCLK and disable SYSOSC

To switch MCLK from LFCLK to SYSOSC in RUN mode:

  1. Verify that MCLK is sourced from LFCLK (CLKSTATUS.CURMCLKSEL is set)
  2. Clear MCLKCFG.USELFCLK or SYSOSCCFG.DISABLE, whichever was set to switch MCLK to LFCLK

To switch MCLK from SYSOSC to HSCLK:

  1. Verify that MCLK is sourced from SYSOSC (CLKSTATUS.HSCLKMUX is cleared).
  2. Enable the desired high speed sources (SYSPLL, HFXT, HFCLK_IN) according to their respective requirements.
  3. Select the desired HSCLK source through the HSCLKCFG.HSCLKSEL control
  4. Verify that CLKSTATUS.HSCLKGOOD is set, indicating that the selected HSCLK source is valid.
  5. Set MCLKCFG.USEHSCLK to switch MCLK to HSCLK.

To switch MCLK from HSCLK to SYSOSC:

  1. Verify that MCLK is sourced from HSCLK (CLKSTATUS.HSCLKMUX is set).
  2. Clear MCLKCFG.USEHSCLK to switch MCLK to SYSOSC.
  3. Wait for CLKSTATUS.HSCLKMUX to clear, indicating that MCLK is now sourced from SYSOSC.
  4. If desired, disable any high-speed clock sources (SYSPLL or HFXT)

As shown in Table 2-7, the USELFCLK and USEHSCLK bits in MCLKCFG are mutually exclusive and must not be set at the same time. To switch MCLK from LFCLK to HSCLK, or HSCLK to LFCLK, MCLK is first switched to SYSOSC before switching to the final clock source. The procedures below describe how to switch MCLK from HSCLK to LFCK or from LFCK to HSCLK.

To switch MCLK from HSCLK to LFCLK:

  1. Verify that MCLK is sourced from HSCLK (CLKSTATUS.HSCLKMUX is set).
  2. Clear MCLKCFG.USEHSCLK to switch MCLK to SYSOSC
  3. Wait for CLKSTATUS.HSCLKMUX to clear, indicating that MCLK is now sourced from SYSOSC
  4. Disable any high speed sources (SYSPLL, HFXT, HFCLK_IN) which were enabled
  5. Wait for CLKSTATUS.HSCLKSOFF to be asserted, indicating that high-speed clocks are off
  6. Set MCLKCFG.USELFCLK to switch MCLK to LFCLK while leaving SYSOSC enabled, or set SYSOSCCFG.DISABLE to switch MCLK to LFCLK and disable SYSOSC

To switch MCLK from LFCLK to HSCLK:

  1. Verify that MCLK is sourced from LFCLK (CLKSTATUS.CURMCLKSEL is set)
  2. Clear SYSOSCCFG.DISABLE or MCLKCFG.USELFCLK, based on which was set previously
  3. Wait for CLKSTATUS.CURMCLKSEL to clear, indicating that MCLK is now sourced from SYSOSC
  4. Enable the desired high speed oscillators (SYSPLL, HFXT, HFCLK_IN) according to their respective requirements
  5. Select the desired HSCLK source through the HSCLKCFG.HSCLKSEL control
  6. Verify that CLKSTATUS.HSCLKGOOD is set, indicating that the selected HSCLK source is valid
  7. Set MCLKCFG.USEHSCLK to switch MCLK to HSCLK
Note: When MCLK is actively sourced by HSCLK (the HSCLKMUX bit in the CLKSTATUS register is set), the HSCLK source selection must not be changed (the HSCLKSEL bit in the HSCLKCFG register and the MCLK2XVCO bit in the SYSPLLCFG0 register must not be changed). To change the HSCLK source, first switch MCLK to SYSOSC using the procedure given above, re-configure the HSCLK source, and then switch MCLK back to HSCLK.

MCLK Divider (MDIV)

An MCLK source divider (MDIV) is provided to enable MCLK operation in between the lowest SYSOSC frequency (4MHz) and the LFCLK frequency (32kHz). MDIV is for applications with a limited peak current but that still require a higher clock speed than 32kHz. MDIV supports dividing the 4MHz SYSOSC frequency by up to 16, enabling the additional MCLK frequency options given in Table 2-8. For example, a 500kHz MCLK frequency can be obtained by setting SYSOSC to 4MHz and setting MDIV to 7 (divide-by-8).

Table 2-8 shows the MCLK frequency which is realized with /2, /4, /8, and /16 MDIV configurations, but MDIV can be set to any integer divider between /2 and /16 (MDIV register values of 0x1 through 0xF, respectively, with 0x0 disabling the MDIV).

Table 2-8 Typical MCLK Configurations for Operation Between 4MHz and 32kHz
MCLK Source MDIV MCLK Frequency
SYSOSC (4MHz) 0 (Disabled) 4MHz
1 (/2) 2MHz
3 (/4) 1MHz
7 (/8) 500kHz
15 (/16) 250kHz

To use MDIV to operate MCLK at an intermediate frequency below 4MHz, follow the steps below:

  1. Disable asynchronous fast clock requests (make sure that the BLOCKASYNCALL bit is set in the in SYSOSCCFG register)
  2. Make sure that SYSOSC is selected as the MCLK source
  3. Set the SYSOSC frequency to 4MHz (set the FREQ field in the SYSOSCCFG register to 0x01)
  4. Delay for 10 MCLK cycles
  5. Set the desired divider value in the MDIV field in the MCLKCFG register (from 1 to 15, corresponding to /2 to /16, respectively)

Several rules apply when using MDIV to reduce the MCLK frequency:

  • MDIV must not be used when high speed oscillators are used to source MCLK (SYSPLL, HFCLK); if SYSPLL or HFCLK are selected to source MCLK, MDIV must be disabled (MCLKCFG.MDIV=0x00)
  • The SYSOSC frequency must be kept at 4MHz when MDIV is enabled
  • Asynchronous requests to change the SYSOSC frequency must remain blocked

To disable MDIV:

  1. Disable MDIV (set the MDIV field in the MCLKCFG register to 0x0)
  2. Wait for 16 MCLK cycles before changing the SYSOSC frequency from 4MHz to another frequency
Note: MDIV does not apply to LFCLK, as MDIV is not in the LFCLK path when LFCLK is selected as the MCLK source. If LFCLK is selected for MCLK, MDIV must be disabled.