SLAU847D October 2022 – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228 , MSPM0L2228-Q1
Table 15-5 lists the memory-mapped registers for the COMP registers. All register offset addresses not listed in Table 15-5 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
400h | FSUB_0 | Subscriber Port 0 | Go | |
404h | FSUB_1 | Subscriber Port 1 | Go | |
444h | FPUB_1 | Publisher port 1 | Go | |
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
808h | CLKCFG | Peripheral Clock Configuration Register | Go | |
814h | STAT | Status Register | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt index | GEN_EVENT | Go |
1058h | IMASK | Interrupt mask | GEN_EVENT | Go |
1060h | RIS | Raw interrupt status | GEN_EVENT | Go |
1068h | MIS | Masked interrupt status | GEN_EVENT | Go |
1070h | ISET | Interrupt set | GEN_EVENT | Go |
1078h | ICLR | Interrupt clear | GEN_EVENT | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | CTL0 | Control 0 | Go | |
1104h | CTL1 | Control 1 | Go | |
1108h | CTL2 | Control 2 | Go | |
110Ch | CTL3 | Control 3 | Go | |
1120h | STAT | Status | Go |
Complex bit access types are encoded to fit into small table cells. Table 15-6 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
K | K | Write protected by a key |
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
FSUB_0 is shown in Figure 15-5 and described in Table 15-7.
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Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W- | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FSUB_1 is shown in Figure 15-6 and described in Table 15-8.
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Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W- | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FPUB_1 is shown in Figure 15-7 and described in Table 15-9.
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Publisher port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
PWREN is shown in Figure 15-8 and described in Table 15-10.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W- | K-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | K | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 15-9 and described in Table 15-11.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W- | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
CLKCFG is shown in Figure 15-10 and described in Table 15-12.
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Peripheral Clock Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BLOCKASYNC | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to Allow State Change -- 0xA9
A9h = Key value to be used in writing to this register for the write to take effect. |
23-9 | RESERVED | R/W | 0h | |
8 | BLOCKASYNC | R/W | 0h | Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0h = disable COMP to request SYSOSC 1h = enable COMP to request SYSOSC |
7-0 | RESERVED | R/W | 0h |
STAT is shown in Figure 15-11 and described in Table 15-13.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
IIDX is shown in Figure 15-12 and described in Table 15-14.
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Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 2h = Comparator output interrupt 3h = Comparator output inverted interrupt 4h = Comparator output ready interrupt |
IMASK is shown in Figure 15-13 and described in Table 15-15.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | OUTRDYIFG | R/W | 0h | Masks OUTRDYIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
2 | COMPINVIFG | R/W | 0h | Masks COMPINVIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
1 | COMPIFG | R/W | 0h | Masks COMPIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | RESERVED | R/W | 0h |
RIS is shown in Figure 15-14 and described in Table 15-16.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | OUTRDYIFG | R | 0h | Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid.
0h = No interrupt pending 1h = Interrupt pending |
2 | COMPINVIFG | R | 0h | Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0h = No interrupt pending 1h = Interrupt pending |
1 | COMPIFG | R | 0h | Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0h = No interrupt pending 1h = Interrupt pending |
0 | RESERVED | R | 0h |
MIS is shown in Figure 15-15 and described in Table 15-17.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | OUTRDYIFG | R | 0h | Masked interrupt status for OUTRDYIFG
0h = OUTRDYIFG does not request an interrupt service routine 1h = OUTRDYIFG requests an interrupt service routine |
2 | COMPINVIFG | R | 0h | Masked interrupt status for COMPINVIFG
0h = COMPINVIFG does not request an interrupt service routine 1h = COMPINVIFG requests an interrupt service routine |
1 | COMPIFG | R | 0h | Masked interrupt status for COMPIFG
0h = COMPIFG does not request an interrupt service routine 1h = COMPIFG requests an interrupt service routine |
0 | RESERVED | R | 0h |
ISET is shown in Figure 15-16 and described in Table 15-18.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | OUTRDYIFG | W | 0h | Sets OUTRDYIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to OUTRDYIFG is set |
2 | COMPINVIFG | W | 0h | Sets COMPINVIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPINVIFG is set |
1 | COMPIFG | W | 0h | Sets COMPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPIFG is set |
0 | RESERVED | W | 0h |
ICLR is shown in Figure 15-17 and described in Table 15-19.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | OUTRDYIFG | W | 0h | Clears OUTRDYIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to OUTRDYIFG is cleared |
2 | COMPINVIFG | W | 0h | Clears COMPINVIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPINVIFG is cleared |
1 | COMPIFG | W | 0h | Clears COMPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPIFG is cleared |
0 | RESERVED | W | 0h |
IIDX is shown in Figure 15-18 and described in Table 15-20.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 2h = Comparator output interrupt 3h = Comparator output inverted interrupt 4h = Comparator output ready interrupt |
IMASK is shown in Figure 15-19 and described in Table 15-21.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | OUTRDYIFG | R/W | 0h | Masks OUTRDYIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
2 | COMPINVIFG | R/W | 0h | Masks COMPINVIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
1 | COMPIFG | R/W | 0h | Masks COMPIFG
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | RESERVED | R/W | 0h |
RIS is shown in Figure 15-20 and described in Table 15-22.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | OUTRDYIFG | R | 0h | Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid.
0h = No interrupt pending 1h = Interrupt pending |
2 | COMPINVIFG | R | 0h | Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0h = No interrupt pending 1h = Interrupt pending |
1 | COMPIFG | R | 0h | Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit.
0h = No interrupt pending 1h = Interrupt pending |
0 | RESERVED | R | 0h |
MIS is shown in Figure 15-21 and described in Table 15-23.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | OUTRDYIFG | R | 0h | Masked interrupt status for OUTRDYIFG
0h = OUTRDYIFG does not request an interrupt service routine 1h = OUTRDYIFG requests an interrupt service routine |
2 | COMPINVIFG | R | 0h | Masked interrupt status for COMPINVIFG
0h = COMPINVIFG does not request an interrupt service routine 1h = COMPINVIFG requests an interrupt service routine |
1 | COMPIFG | R | 0h | Masked interrupt status for COMPIFG
0h = COMPIFG does not request an interrupt service routine 1h = COMPIFG requests an interrupt service routine |
0 | RESERVED | R | 0h |
ISET is shown in Figure 15-22 and described in Table 15-24.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | OUTRDYIFG | W | 0h | Sets OUTRDYIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to OUTRDYIFG is set |
2 | COMPINVIFG | W | 0h | Sets COMPINVIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPINVIFG is set |
1 | COMPIFG | W | 0h | Sets COMPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPIFG is set |
0 | RESERVED | W | 0h |
ICLR is shown in Figure 15-23 and described in Table 15-25.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUTRDYIFG | COMPINVIFG | COMPIFG | RESERVED | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | OUTRDYIFG | W | 0h | Clears OUTRDYIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to OUTRDYIFG is cleared |
2 | COMPINVIFG | W | 0h | Clears COMPINVIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPINVIFG is cleared |
1 | COMPIFG | W | 0h | Clears COMPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to COMPIFG is cleared |
0 | RESERVED | W | 0h |
EVT_MODE is shown in Figure 15-24 and described in Table 15-26.
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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT1_CFG | INT0_CFG | |||||
R/W-0h | R-2h | R-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-2 | EVT1_CFG | R | 2h | Event line mode select for event corresponding to GEN_EVENT
0h = The interrupt or event line is disabled. 1h = Event handled by software. Software must clear the associated RIS flag. 2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 1h | Event line mode select for event corresponding to CPU_INT
0h = The interrupt or event line is disabled. 1h = Event handled by software. Software must clear the associated RIS flag. 2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 15-25 and described in Table 15-27.
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This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-611h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | RESERVED | MAJREV | MINREV | ||||||||||||
R-0h | R- | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 611h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance* |
11-8 | RESERVED | R | 0h | |
7-4 | MAJREV | R | 0h | Major rev of the IP |
3-0 | MINREV | R | 0h | Minor rev of the IP |
CTL0 is shown in Figure 15-26 and described in Table 15-28.
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Control 0 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IMEN | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | IMSEL | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IPEN | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IPSEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IMEN | R/W | 0h | Channel input enable for the negative terminal of the comparator.
0h = Selected analog input channel for negative terminal is disabled 1h = Selected analog input channel for negative terminal is enabled |
30-19 | RESERVED | R/W | 0h | |
18-16 | IMSEL | R/W | 0h | Channel input selected for the negative terminal of the comparator if IMEN is set to 1.
0h = Channel 0 selected 1h = Channel 1 selected 2h = Channel 2 selected 3h = Channel 3 selected 4h = Channel 4 selected 5h = Channel 5 selected 6h = Channel 6 selected 7h = Channel 7 selected |
15 | IPEN | R/W | 0h | Channel input enable for the positive terminal of the comparator.
0h = Selected analog input channel for positive terminal is disabled 1h = Selected analog input channel for positive terminal is enabled |
14-3 | RESERVED | R/W | 0h | |
2-0 | IPSEL | R/W | 0h | Channel input selected for the positive terminal of the comparator if IPEN is set to 1.
0h = Channel 0 selected 1h = Channel 1 selected 2h = Channel 2 selected 3h = Channel 3 selected 4h = Channel 4 selected 5h = Channel 5 selected 6h = Channel 6 selected 7h = Channel 7 selected |
CTL1 is shown in Figure 15-27 and described in Table 15-29.
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Control 1 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WINCOMPEN | RESERVED | FLTDLY | FLTEN | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTPOL | HYST | IES | SHORT | EXCH | MODE | ENABLE | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | 0h | |
12 | WINCOMPEN | R/W | 0h | This bit enables window comparator operation of comparator.
0h = window comparator is disable 1h = window comparator is enable |
11 | RESERVED | R/W | 0h | |
10-9 | FLTDLY | R/W | 0h | These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings.
0h = Typical filter delay of 70ns 1h = Typical filter delay of 500ns 2h = Typical filter delay of 1200ns 3h = Typical filter delay of 2700ns |
8 | FLTEN | R/W | 0h | This bit enables the analog filter at comparator output.
0h = Comparator output filter is disabled 1h = Comparator output filter is enabled |
7 | OUTPOL | R/W | 0h | This bit selects the comparator output polarity.
0h = Comparator output is noninverted 1h = Comparator output is inverted |
6-5 | HYST | R/W | 0h | These bits select the hysteresis setting of the comparator.
0h = No hysteresis 1h = Low hysteresis, typical 10mV 2h = Medium hysteresis, typical 20mV 3h = High hysteresis, typical 30mV |
4 | IES | R/W | 0h | This bit selected the interrupt edge for COMPIFG and COMPINVIFG.
0h = Rising edge sets COMPIFG and falling edge sets COMPINVIFG 1h = Falling edge sets COMPIFG and rising edge sets COMPINVIFG |
3 | SHORT | R/W | 0h | This bit shorts the positive and negative input terminals of the comparator.
0h = Comparator positive and negative input terminals are not shorted 1h = Comparator positive and negative input terminals are shorted |
2 | EXCH | R/W | 0h | This bit exchanges the comparator inputs and inverts the comparator output.
0h = Comparator inputs not exchanged and output not inverted 1h = Comparator inputs exchanged and output inverted |
1 | MODE | R/W | 0h | This bit selects the comparator operating mode.
0h = Comparator is in fast mode 1h = Comparator is in ultra-low power mode |
0 | ENABLE | R/W | 0h | This bit turns on the comparator. When the comparator is turned off it consumes no power.
0h = Comparator is off 1h = Comparator is on |
CTL2 is shown in Figure 15-28 and described in Table 15-30.
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Control 2 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SAMPMODE | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DACSW | DACCTL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BLANKSRC | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REFSEL | RESERVED | REFSRC | RESERVED | REFMODE | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | 0h | |
24 | SAMPMODE | R/W | 0h | Enable sampled mode of comparator.
0h = Sampled mode disabled 1h = Sampled mode enabled |
23-18 | RESERVED | R/W | 0h | |
17 | DACSW | R/W | 0h | This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1.
0h = DACCODE0 selected for 8-bit DAC 1h = DACCODE1 selected for 8-bit DAC |
16 | DACCTL | R/W | 0h | This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1.
0h = Comparator output controls selection between DACCODE0 and DACCODE1 1h = DACSW bit controls selection between DACCODE0 and DACCODE1 |
15-11 | RESERVED | R/W | 0h | |
10-8 | BLANKSRC | R/W | 0h | These bits select the blanking source for the comparator.
0h = Blanking source disabled 1h = Select Blanking Source 1 2h = Select Blanking Source 2 3h = Select Blanking Source 3 4h = Select Blanking Source 4 5h = Select Blanking Source 5 6h = Select Blanking Source 6 |
7 | REFSEL | R/W | 0h | This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator.
0h = If EXCH bit is 0, the selected reference is applied to positive terminal. If EXCH bit is 1, the selected reference is applied to negative terminal. 1h = If EXCH bit is 0, the selected reference is applied to negative terminal. If EXCH bit is 1, the selected reference is applied to positive terminal. |
6 | RESERVED | R/W | 0h | |
5-3 | REFSRC | R/W | 0h | These bits select the reference source for the comparator. 0h = Reference voltage generator is disabled (local reference buffer as well as DAC). 1h = VDDA selected as the reference source to DAC and DAC output applied as reference to comparator. 2h = VREF selected as reference to DAC and DAC output applied as reference to comparator. 3h = In devices where internal VREF is buffered and connected to external VREF pin, VREF applied as reference to comparator. DAC is switched off. 5h = VDDA is used as comparator reference. 6h = Internal reference selected as the reference source to DAC and DAC output applied as reference to comparator. 7h = Internal VREF is used as the source of comparator. Not all devices will have this option. |
2-1 | RESERVED | R/W | 0h | |
0 | REFMODE | R/W | 0h | This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Fast mode operation offers higher accuracy but consumes higher current. Low power operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL > 0. 0h = ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in static mode. 1h = ULP_REF bandgap, local reference buffer and 8-bit DAC inside comparator operate in sampled mode. |
CTL3 is shown in Figure 15-29 and described in Table 15-31.
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Control 3 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DACCODE1 | RESERVED | DACCODE0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | 0h | |
23-16 | DACCODE1 | R/W | 0h | This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be selected reference voltage x 1/256V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256V.
0h = Minimum DAC code value FFh = Minimum DAC code value |
15-8 | RESERVED | R/W | 0h | |
7-0 | DACCODE0 | R/W | 0h | This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be selected reference voltage x 1/256V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256V.
0h = Minimum DAC code value FFh = Minimum DAC code value |
STAT is shown in Figure 15-30 and described in Table 15-32.
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Status register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUT | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | |
0 | OUT | R | 0h | This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output.
0h = Comparator output is low 1h = Comparator output is high |