SLAU847D October 2022 – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1
Table 19-12 lists the memory-mapped registers for the UART registers. All register offset addresses not listed in Table 19-12 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
808h | CLKCFG | Peripheral Clock Configuration Register | Go | |
814h | STAT | Status Register | Go | |
1000h | CLKDIV | Clock Divider | Go | |
1008h | CLKSEL | Clock Select for Ultra Low Power peripherals | Go | |
1018h | PDBGCTL | Peripheral Debug Control | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt index | DMA_TRIG_RX | Go |
1058h | IMASK | Interrupt mask | DMA_TRIG_RX | Go |
1060h | RIS | Raw interrupt status | DMA_TRIG_RX | Go |
1068h | MIS | Masked interrupt status | DMA_TRIG_RX | Go |
1070h | ISET | Interrupt set | DMA_TRIG_RX | Go |
1078h | ICLR | Interrupt clear | DMA_TRIG_RX | Go |
1080h | IIDX | Interrupt index | DMA_TRIG_TX | Go |
1088h | IMASK | Interrupt mask | DMA_TRIG_TX | Go |
1090h | RIS | Raw interrupt status | DMA_TRIG_TX | Go |
1098h | MIS | Masked interrupt status | DMA_TRIG_TX | Go |
10A0h | ISET | Interrupt set | DMA_TRIG_TX | Go |
10A8h | ICLR | Interrupt clear | DMA_TRIG_TX | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10E4h | INTCTL | Interrupt control register | Go | |
1100h | CTL0 | UART Control Register 0 | Go | |
1104h | LCRH | UART Line Control Register | Go | |
1108h | STAT | UART Status Register | Go | |
110Ch | IFLS | UART Interrupt FIFO Level Select Register | Go | |
1110h | IBRD | UART Integer Baud-Rate Divisor Register | Go | |
1114h | FBRD | UART Fractional Baud-Rate Divisor Register | Go | |
1118h | GFCTL | Glitch Filter Control | Go | |
1120h | TXDATA | UART Transmit Data Register | Go | |
1124h | RXDATA | UART Receive Data Register | Go | |
1130h | LINCNT | UART LIN Mode Counter Register | Go | |
1134h | LINCTL | UART LIN Mode Control Register | Go | |
1138h | LINC0 | UART LIN Mode Capture 0 Register | Go | |
113Ch | LINC1 | UART LIN Mode Capture 1 Register | Go | |
1140h | IRCTL | eUSCI_Ax IrDA Control Word Register | Go | |
1148h | AMASK | Self Address Mask Register | Go | |
114Ch | ADDR | Self Address Register | Go | |
1160h | CLKDIV2 | Clock Divider | Go |
Complex bit access types are encoded to fit into small table cells. Table 19-13 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WK | W K |
Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 19-16 and described in Table 19-14.
Return to the Summary Table.
Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change 26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power
KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 19-17 and described in Table 19-15.
Return to the Summary Table.
Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
CLKCFG is shown in Figure 19-18 and described in Table 19-16.
Return to the Summary Table.
Peripheral Clock Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BLOCKASYNC | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to Allow State Change -- 0xA9 A9h = 0xA9 |
23-9 | RESERVED | R/W | 0h | |
8 | BLOCKASYNC | R/W | 0h | Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0h = 0 1h = 1 |
7-0 | RESERVED | R/W | 0h |
STAT is shown in Figure 19-19 and described in Table 19-17.
Return to the Summary Table.
Reset status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKDIV is shown in Figure 19-20 and described in Table 19-18.
Return to the Summary Table.
This register is used to specify module-specific divide ratio of the functional clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |
CLKSEL is shown in Figure 19-21 and described in Table 19-19.
Return to the Summary Table.
Clock source selection for peripherals
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSCLK_SEL | MFCLK_SEL | LFCLK_SEL | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | BUSCLK_SEL | R/W | 0h | Selects BUS CLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
2 | MFCLK_SEL | R/W | 0h | Selects MFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
1 | LFCLK_SEL | R/W | 0h | Selects LFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
0 | RESERVED | R/W | 0h |
PDBGCTL is shown in Figure 19-22 and described in Table 19-20.
Return to the Summary Table.
This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W- | R/W-1h | R/W-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | SOFT | R/W | 1h | Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption |
0 | FREE | R/W | 1h | Free run control 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input |
IIDX is shown in Figure 19-23 and described in Table 19-21.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least
priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full
set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt
flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved 00h = No interrupt pending 01h = UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 02h = UART framing error interrupt; Interrupt Flag: FE 03h = UART parity error interrupt; Interrupt Flag: PE 04h = UART break error interrupt; Interrupt Flag: BE 05h = UART receive overrun error interrupt; Interrupt Flag: OE 06h = Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE 07h = Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE 08h = LIN capture 0 / match interrupt; Interrupt Flag: LINC0 09h = LIN capture 1 interrupt; Interrupt Flag: LINC1 0Ah = LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF 0Bh = UART receive interrupt; Interrupt Flag: RX 0Ch = UART transmit interrupt; Interrupt Flag: TX 0Dh = UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT 0Eh = 9-bit mode address match interrupt; Interrupt Flag: MODE_9B Fh = UART Clear to Send Modem interrupt; Interrupt Flag: CTS 10h = DMA DONE on RX 11h = DMA DONE on TX 12h = Noise Error Event |
IMASK is shown in Figure 19-24 and described in Table 19-22.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NERR | DMA_DONE_TX | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_DONE_RX | CTS | ADDR_MATCH | EOT | TXINT | RXINT | LINOVF | LINC1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINC0 | RXPE | RXNE | OVRERR | BRKERR | PARERR | FRMERR | RTOUT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | |
17 | NERR | R/W | 0h | Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
16 | DMA_DONE_TX | R/W | 0h | Enable DMA Done on TX Event Channel Interrupt 0h = Interrupt disabled 1h = Set Interrupt Mask |
15 | DMA_DONE_RX | R/W | 0h | Enable DMA Done on RX Event Channel Interrupt 0h = Interrupt disabled 1h = Set Interrupt Mask |
14 | CTS | R/W | 0h | Enable UART Clear to Send Modem Interrupt. 0h = Interrupt disabled 1h = Set Interrupt Mask |
13 | ADDR_MATCH | R/W | 0h | Enable Address Match Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
12 | EOT | R/W | 0h | Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
11 | TXINT | R/W | 0h | Enable UART Transmit Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
10 | RXINT | R/W | 0h | Enable UART Receive Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | LINOVF | R/W | 0h | Enable LIN Hardware Counter Overflow Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | LINC1 | R/W | 0h | Enable LIN Capture 1 Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | LINC0 | R/W | 0h | Enable LIN Capture 0 / Match Interrupt . 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | RXPE | R/W | 0h | Enable Positive Edge on UARTxRXD Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | RXNE | R/W | 0h | Enable Negative Edge on UARTxRXD Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | OVRERR | R/W | 0h | Enable UART Receive Overrun Error Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3 | BRKERR | R/W | 0h | Enable UART Break Error Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | PARERR | R/W | 0h | Enable UART Parity Error Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | FRMERR | R/W | 0h | Enable UART Framing Error Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | RTOUT | R/W | 0h | Enable UARTOUT Receive Time-Out Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 19-25 and described in Table 19-23.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NERR | DMA_DONE_TX | |||||
R- | R-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_DONE_RX | CTS | ADDR_MATCH | EOT | TXINT | RXINT | LINOVF | LINC1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINC0 | RXPE | RXNE | OVRERR | BRKERR | PARERR | FRMERR | RTOUT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | |
17 | NERR | R | 0h | Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0h = Interrupt did not occur 1h = Interrupt occurred |
16 | DMA_DONE_TX | R | 0h | DMA Done on TX Event Channel Interrupt 0h = Interrupt disabled 1h = Interrupt occurred |
15 | DMA_DONE_RX | R | 0h | DMA Done on RX Event Channel Interrupt 0h = Interrupt disabled 1h = Interrupt occurred |
14 | CTS | R | 0h | UART Clear to Send Modem Interrupt. 0h = Interrupt disabled 1h = Interrupt occurred |
13 | ADDR_MATCH | R | 0h | Address Match Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
12 | EOT | R | 0h | UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer. 0h = Interrupt did not occur 1h = Interrupt occurred |
11 | TXINT | R | 0h | UART Transmit Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
10 | RXINT | R | 0h | UART Receive Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
9 | LINOVF | R | 0h | LIN Hardware Counter Overflow Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
8 | LINC1 | R | 0h | LIN Capture 1 Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
7 | LINC0 | R | 0h | LIN Capture 0 / Match Interrupt . 0h = Interrupt did not occur 1h = Interrupt occurred |
6 | RXPE | R | 0h | Positive Edge on UARTxRXD Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
5 | RXNE | R | 0h | Negative Edge on UARTxRXD Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
4 | OVRERR | R | 0h | UART Receive Overrun Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
3 | BRKERR | R | 0h | UART Break Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | PARERR | R | 0h | UART Parity Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
1 | FRMERR | R | 0h | UART Framing Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RTOUT | R | 0h | UARTOUT Receive Time-Out Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Figure 19-26 and described in Table 19-24.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NERR | DMA_DONE_TX | |||||
R-0h | R-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_DONE_RX | CTS | ADDR_MATCH | EOT | TXINT | RXINT | LINOVF | LINC1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINC0 | RXPE | RXNE | OVRERR | BRKERR | PARERR | FRMERR | RTOUT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | |
17 | NERR | R | 0h | Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0h = Interrupt did not occur 1h = Interrupt occurred |
16 | DMA_DONE_TX | R | 0h | Masked DMA Done on TX Event Channel Interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
15 | DMA_DONE_RX | R | 0h | Masked DMA Done on RX Event Channel Interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
14 | CTS | R | 0h | Masked UART Clear to Send Modem Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
13 | ADDR_MATCH | R | 0h | Masked Address Match Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
12 | EOT | R | 0h | UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer. 0h = Interrupt did not occur 1h = Interrupt occurred |
11 | TXINT | R | 0h | Masked UART Transmit Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
10 | RXINT | R | 0h | Masked UART Receive Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
9 | LINOVF | R | 0h | Masked LIN Hardware Counter Overflow Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
8 | LINC1 | R | 0h | Masked LIN Capture 1 Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
7 | LINC0 | R | 0h | Masked LIN Capture 0 / Match Interrupt . 0h = Interrupt did not occur 1h = Interrupt occurred |
6 | RXPE | R | 0h | Masked Positive Edge on UARTxRXD Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
5 | RXNE | R | 0h | Masked Negative Edge on UARTxRXD Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
4 | OVRERR | R | 0h | Masked UART Receive Overrun Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
3 | BRKERR | R | 0h | Masked UART Break Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | PARERR | R | 0h | Masked UART Parity Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
1 | FRMERR | R | 0h | Masked UART Framing Error Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RTOUT | R | 0h | Masked UARTOUT Receive Time-Out Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
ISET is shown in Figure 19-27 and described in Table 19-25.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NERR | DMA_DONE_TX | |||||
W-0h | W-0h | W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_DONE_RX | CTS | ADDR_MATCH | EOT | TXINT | RXINT | LINOVF | LINC1 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINC0 | RXPE | RXNE | OVRERR | BRKERR | PARERR | FRMERR | RTOUT |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | W | 0h | |
17 | NERR | W | 0h | Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0h = Writing this has no effect 1h = Set the interrupt |
16 | DMA_DONE_TX | W | 0h | Set DMA Done on TX Event Channel Interrupt 0h = Interrupt disabled 1h = Set Interrupt |
15 | DMA_DONE_RX | W | 0h | Set DMA Done on RX Event Channel Interrupt 0h = Interrupt disabled 1h = Set Interrupt |
14 | CTS | W | 0h | Set UART Clear to Send Modem Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
13 | ADDR_MATCH | W | 0h | Set Address Match Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
12 | EOT | W | 0h | Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer. 0h = Writing 0 has no effect 1h = Set Interrupt |
11 | TXINT | W | 0h | Set UART Transmit Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
10 | RXINT | W | 0h | Set UART Receive Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
9 | LINOVF | W | 0h | Set LIN Hardware Counter Overflow Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
8 | LINC1 | W | 0h | Set LIN Capture 1 Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
7 | LINC0 | W | 0h | Set LIN Capture 0 / Match Interrupt . 0h = Writing 0 has no effect 1h = Set Interrupt |
6 | RXPE | W | 0h | Set Positive Edge on UARTxRXD Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
5 | RXNE | W | 0h | Set Negative Edge on UARTxRXD Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
4 | OVRERR | W | 0h | Set UART Receive Overrun Error Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
3 | BRKERR | W | 0h | Set UART Break Error Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
2 | PARERR | W | 0h | Set UART Parity Error Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
1 | FRMERR | W | 0h | Set UART Framing Error Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
0 | RTOUT | W | 0h | Set UARTOUT Receive Time-Out Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
ICLR is shown in Figure 19-28 and described in Table 19-26.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NERR | DMA_DONE_TX | |||||
W-0h | W-0h | W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_DONE_RX | CTS | ADDR_MATCH | EOT | TXINT | RXINT | LINOVF | LINC1 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINC0 | RXPE | RXNE | OVRERR | BRKERR | PARERR | FRMERR | RTOUT |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | W | 0h | |
17 | NERR | W | 0h | Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal 0h = Writing 0 has no effect 1h = Clear Interrupt |
16 | DMA_DONE_TX | W | 0h | Clear DMA Done on TX Event Channel Interrupt 0h = Interrupt disabled 1h = Clear Interrupt |
15 | DMA_DONE_RX | W | 0h | Clear DMA Done on RX Event Channel Interrupt 0h = Interrupt disabled 1h = Clear Interrupt |
14 | CTS | W | 0h | Clear UART Clear to Send Modem Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
13 | ADDR_MATCH | W | 0h | Clear Address Match Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
12 | EOT | W | 0h | Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer. 0h = Writing 0 has no effect 1h = Clear Interrupt |
11 | TXINT | W | 0h | Clear UART Transmit Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
10 | RXINT | W | 0h | Clear UART Receive Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
9 | LINOVF | W | 0h | Clear LIN Hardware Counter Overflow Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
8 | LINC1 | W | 0h | Clear LIN Capture 1 Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
7 | LINC0 | W | 0h | Clear LIN Capture 0 / Match Interrupt . 0h = Writing 0 has no effect 1h = Clear Interrupt |
6 | RXPE | W | 0h | Clear Positive Edge on UARTxRXD Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
5 | RXNE | W | 0h | Clear Negative Edge on UARTxRXD Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
4 | OVRERR | W | 0h | Clear UART Receive Overrun Error Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
3 | BRKERR | W | 0h | Clear UART Break Error Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
2 | PARERR | W | 0h | Clear UART Parity Error Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
1 | FRMERR | W | 0h | Clear UART Framing Error Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
0 | RTOUT | W | 0h | Clear UARTOUT Receive Time-Out Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
IIDX is shown in Figure 19-29 and described in Table 19-27.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least
priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full
set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt
flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest 0Bh = UART receive interrupt; Interrupt Flag: RX |
IMASK is shown in Figure 19-30 and described in Table 19-28.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXINT | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RTOUT | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R/W | 0h | |
10 | RXINT | R/W | 0h | Enable UART Receive Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9-1 | RESERVED | R/W | 0h | |
0 | RTOUT | R/W | 0h | Enable UARTOUT Receive Time-Out Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 19-31 and described in Table 19-29.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXINT | RESERVED | |||||
R- | R-0h | R- | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RTOUT | ||||||
R- | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | |
10 | RXINT | R | 0h | UART Receive Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
9-1 | RESERVED | R | 0h | |
0 | RTOUT | R | 0h | UARTOUT Receive Time-Out Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Figure 19-32 and described in Table 19-30.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXINT | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RTOUT | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | |
10 | RXINT | R | 0h | Masked UART Receive Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
9-1 | RESERVED | R | 0h | |
0 | RTOUT | R | 0h | Masked UARTOUT Receive Time-Out Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
ISET is shown in Figure 19-33 and described in Table 19-31.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXINT | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RTOUT | ||||||
W-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | W | 0h | |
10 | RXINT | W | 0h | Set UART Receive Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
9-1 | RESERVED | W | 0h | |
0 | RTOUT | W | 0h | Set UARTOUT Receive Time-Out Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
ICLR is shown in Figure 19-34 and described in Table 19-32.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXINT | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RTOUT | ||||||
W-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | W | 0h | |
10 | RXINT | W | 0h | Clear UART Receive Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
9-1 | RESERVED | W | 0h | |
0 | RTOUT | W | 0h | Clear UARTOUT Receive Time-Out Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
IIDX is shown in Figure 19-35 and described in Table 19-33.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least
priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full
set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt
flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved 00h = No interrupt pending 0Ch = UART transmit interrupt; Interrupt Flag: TX |
IMASK is shown in Figure 19-36 and described in Table 19-34.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TXINT | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | 0h | |
11 | TXINT | R/W | 0h | Enable UART Transmit Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
10-0 | RESERVED | R/W | 0h |
RIS is shown in Figure 19-37 and described in Table 19-35.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TXINT | RESERVED | |||||
R- | R-0h | R- | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | |
11 | TXINT | R | 0h | UART Transmit Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
10-0 | RESERVED | R | 0h |
MIS is shown in Figure 19-38 and described in Table 19-36.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TXINT | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | |
11 | TXINT | R | 0h | Masked UART Transmit Interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
10-0 | RESERVED | R | 0h |
ISET is shown in Figure 19-39 and described in Table 19-37.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TXINT | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | W | 0h | |
11 | TXINT | W | 0h | Set UART Transmit Interrupt. 0h = Writing 0 has no effect 1h = Set Interrupt |
10-0 | RESERVED | W | 0h |
ICLR is shown in Figure 19-40 and described in Table 19-38.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TXINT | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | W | 0h | |
11 | TXINT | W | 0h | Clear UART Transmit Interrupt. 0h = Writing 0 has no effect 1h = Clear Interrupt |
10-0 | RESERVED | W | 0h |
EVT_MODE is shown in Figure 19-41 and described in Table 19-39.
Return to the Summary Table.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT2_CFG | INT1_CFG | INT0_CFG | ||||
R/W- | R-2h | R-2h | R-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5-4 | INT2_CFG | R | 2h | Event line mode select for event corresponding to DMA_TRIG_TX 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
3-2 | INT1_CFG | R | 2h | Event line mode select for event corresponding to DMA_TRIG_RX 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 1h | Event line mode select for event corresponding to CPU_INT 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
INTCTL is shown in Figure 19-42 and described in Table 19-40.
Return to the Summary Table.
Interrupt control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTEVAL | ||||||
R/W- | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | INTEVAL | W | 0h | Writing a 1 to this field re-evaluates the interrupt sources. 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. |
CTL0 is shown in Figure 19-43 and described in Table 19-41.
Return to the Summary Table.
UART Control Register
The CTL0 register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE)
bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled
during a transmit or receive operation, the current transaction is completed prior to the UART stopping. NOTE: The CTL0 register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence
is recommended for making changes to the CTL0 register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit FEN in the UART control register CTL0.
4. Reprogram the control register.
5. Enable the UART.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MSBFIRST | MAJVOTE | FEN | HSE | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HSE | CTSEN | RTSEN | RTS | RESERVED | MODE | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MENC | TXD_OUT | TXD_OUT_EN | TXE | RXE | LBE | RESERVED | ENABLE |
R/W-0h | R/W-0h | R/W-1h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | 0h | |
19 | MSBFIRST | R/W | 0h | Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit. 0h = Least significant bit is sent first in the protocol packet 1h = Most significant bit is sent first in the protocol packet |
18 | MAJVOTE | R/W | 0h | Majority Vote Enable When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set. Oversampling of 16 : bits 7, 8, 9 are used Oversampling of 8 : bits 3, 4, 5 are used Disabled : Single sample value (center value) used 0h = Majority voting is disabled 1h = Majority voting is enabled |
17 | FEN | R/W | 0h | UART Enable FIFOs 0h = The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 1h = The transmit and receive FIFO buffers are enabled (FIFO mode). |
16-15 | HSE | R/W | 0h | High-Speed Bit Oversampling Enable NOTE: The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART
bit is set). 0h = 16x oversampling. 1h = 8x oversampling. 2h = 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled. |
14 | CTSEN | R/W | 0h | Enable Clear To Send 0h = CTS hardware flow control is disabled. 1h = CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted. |
13 | RTSEN | R/W | 0h | Enable hardware controlled Request to Send 0h = RTS hardware flow control is disabled. 1h = RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries. |
12 | RTS | R/W | 0h | Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output. 0h = Signal not RTS 1h = Signal RTS |
11 | RESERVED | R/W | 0h | |
10-8 | MODE | R/W | 0h | Set the communication mode and protocol used. (Not defined settings uses the default setting: 0) 0h = Normal operation 1h = RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data. 2h = The UART operates in IDLE Line Mode 3h = The UART operates in 9 Bit Address mode 4h = ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2. 5h = DALI Mode: |
7 | MENC | R/W | 0h | Manchester Encode enable 0h = Disable Manchester Encoding 1h = Enable Manchester Encoding |
6 | TXD_OUT | R/W | 0h | TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0. 0h = TXD pin is low 1h = TXD pin is high |
5 | TXD_OUT_EN | R/W | 1h | TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 0h = TXD pin can not be controlled by TXD_OUT 1h = TXD pin can be controlled by TXD_OUT |
4 | TXE | R/W | 1h | UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. NOTE: To enable transmission, the UARTEN bit must be set. 0h = The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled. 1h = The transmit section of the UART is enabled. |
3 | RXE | R/W | 1h | UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. NOTE: To enable reception, the UARTEN bit must be set. 0h = The receive section of the UART is disabled. 1h = The receive section of the UART is enabled. |
2 | LBE | R/W | 0h | UART Loop Back Enable 0h = Normal operation. 1h = The UARTxTX path is fed through the UARTxRX path internally. |
1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/W | 0h | UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state. 0h = Disable Module 1h = Enable module |
LCRH is shown in Figure 19-44 and described in Table 19-42.
Return to the Summary Table.
UART Line Control Register The LCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD or UARTIFRD), the LCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the LCRH register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EXTDIR_HOLD | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EXTDIR_HOLD | EXTDIR_SETUP | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SENDIDLE | SPS | WLEN | STP2 | EPS | PEN | BRK | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | 0h | |
25-21 | EXTDIR_HOLD | R/W | 0h | Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.) 0h = Smallest value 1Fh = Highest possible value |
20-16 | EXTDIR_SETUP | R/W | 0h | Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send 0h = Smallest value 1Fh = Highest possible value |
15-8 | RESERVED | R/W | 0h | |
7 | SENDIDLE | R/W | 0h | UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterward. 0h = Disable Send Idle Pattern 1h = Enable Send Idle Pattern |
6 | SPS | R/W | 0h | UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1. 0h = Disable Stick Parity 1h = Enable Stick Parity |
5-4 | WLEN | R/W | 0h | UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0h = 5 bits (default) 1h = 6 bits 2h = 7 bits 3h = 8 bits |
3 | STP2 | R/W | 0h | UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2. 0h = One stop bit is transmitted at the end of a frame. 1h = Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid. |
2 | EPS | R/W | 0h | UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The
transferred byte is a data byte 1 = The transferred byte is an address byte 0h = Odd parity is performed, which checks for an odd number of 1s. 1h = Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. |
1 | PEN | R/W | 0h | UART Parity Enable 0h = Parity is disabled and no parity bit is added to the data frame. 1h = Parity checking and generation is enabled. |
0 | BRK | R/W | 0h | UART Send Break (for LIN Protocol) 0h = Normal use. 1h = A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods). |
STAT is shown in Figure 19-45 and described in Table 19-43.
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UART Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IDLE | CTS | |||||
R- | R-0h | R-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFF | TXFE | RESERVED | RXFF | RXFE | RESERVED | BUSY | |
R-0h | R-1h | R- | R-0h | R-1h | R- | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | |
9 | IDLE | R | 0h | IDLE mode has been detected in Idleline-Multiprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. 0h = IDLE has not been detected before last received character. (In idle-line multiprocessor mode). 1h = IDLE has been detected before last received character. (In idle-line multiprocessor mode). |
8 | CTS | R | 1h | Clear To Send 0h = The CTS signal is not asserted (high). 1h = The CTS signal is asserted (low). |
7 | TXFF | R | 0h | UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0h = The transmitter is not full. 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. |
6 | TXFE | R | 1h | UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0h = The transmitter has data to transmit. 1h = If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty. |
5-4 | RESERVED | R | 0h | |
3 | RXFF | R | 0h | UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0h = The receiver can receive data. 1h = If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full. |
2 | RXFE | R | 1h | UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register. 0h = The receiver is not empty. 1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty. |
1 | RESERVED | R | 0h | |
0 | BUSY | R | 0h | UART Busy This bit is set as soon as the transmit FIFO or TXDATA register becomes nonempty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation. 0h = The UART is not busy. 1h = The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register. |
IFLS is shown in Figure 19-46 and described in Table 19-44.
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The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXTOSEL | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXIFLSEL | RESERVED | TXIFLSEL | ||||
R/W-0h | R/W-2h | R/W-0h | R/W-2h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | 0h | |
11-8 | RXTOSEL | R/W | 0h | UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bit times a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this
function. 0h = Smallest value Fh = Highest possible value |
7 | RESERVED | R/W | 0h | |
6-4 | RXIFLSEL | R/W | 2h | UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used. 0h = RX FIFO >= 1/4 full Note: For ULP Domain 1h = RX FIFO >= 1/4 full 2h = RX FIFO >= 1/2 full (default) 3h = RX FIFO >= 3/4 full 4h = RX FIFO is full Note: For ULP Domain 5h = RX FIFO is full 7h = RX FIFO >= 1 entry available Note: esp. required for DMA Trigger |
3 | RESERVED | R/W | 0h | |
2-0 | TXIFLSEL | R/W | 2h | UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used. 1h = TX FIFO <= 3/4 empty 2h = TX FIFO <= 1/2 empty (default) 3h = TX FIFO <= 1/4 empty 5h = TX FIFO is empty 7h = TX FIFO >= 1 entry free Note: esp. required for DMA Trigger |
IBRD is shown in Figure 19-47 and described in Table 19-45.
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When changing the IBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See Baud-Rate Generation chapter for configuration details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIVINT | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | DIVINT | R/W | 0h | Integer Baud-Rate Divisor 0h = Smallest value FFFFh = Highest possible value |
FBRD is shown in Figure 19-48 and described in Table 19-46.
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UART Fractional Baud-Rate Divisor Register The FBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the FBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See Baud-Rate Generation chapter for configuration details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIVFRAC | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5-0 | DIVFRAC | R/W | 0h | Fractional Baud-Rate Divisor 0h = Smallest value 3Fh = Highest possible value |
GFCTL is shown in Figure 19-49 and described in Table 19-47.
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This register control the glitch filter on the RX input.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHAIN | AGFSEL | AGFEN | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DGFSEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | 0h | |
11 | CHAIN | R/W | 0h | Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling 0h = Disabled 1h = Enabled |
10-9 | AGFSEL | R/W | 0h | Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device data sheet for exact values. 0h = Pulses shorter then 5ns length are filtered. 1h = Pulses shorter then 10ns length are filtered. 2h = Pulses shorter then 25ns length are filtered. 3h = Pulses shorter then 50ns length are filtered. |
8 | AGFEN | R/W | 0h | Analog Glitch Suppression Enable 0h = Analog Glitch Filter disable 1h = Analog Glitch Filter enable |
7-6 | RESERVED | R/W | 0h | |
5-0 | DGFSEL | R/W | 0h | Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The value programmed in this field gives the number of cycles of functional clock up to which the glitch has to be suppressed on the RX line. In IRDA mode: The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK) 0h = Bypass GF 3Fh = Highest Possible Value |
TXDATA is shown in Figure 19-50 and described in Table 19-48.
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UART Transmit Data Register. This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | DATA | R/W | 0h | Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. 0h = Smallest value FFh = Highest possible value |
RXDATA is shown in Figure 19-51 and described in Table 19-49.
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UART Receive Data Register. This register is the data receive register (the interface to the FIFOs). For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NERR | OVRERR | BRKERR | PARERR | FRMERR | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | |
12 | NERR | R | 0h | Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register. 0h = No noise error occurred 1h = Noise error occurred during majority voting |
11 | OVRERR | R | 0h | UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain
valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data to empty the FIFO. 0h = No data has been lost due to a receive overrun. 1h = New data was received but could not be stored, because the previous data was not read (resulting in data loss). |
10 | BRKERR | R | 0h | UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0h = No break condition has occurred 1h = A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). |
9 | PARERR | R | 0h | UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register. 0h = No parity error has occurred 1h = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. |
8 | FRMERR | R | 0h | UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. 0h = No framing error has occurred 1h = The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1). |
7-0 | DATA | R | 0h | Received Data. When read, this field contains the data that was received by the UART. 0h = Smallest value FFh = Highest possible value |
LINCNT is shown in Figure 19-52 and described in Table 19-50.
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UART LIN Mode Counter Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | VALUE | R/W | 0h | 16 bit up counter clocked by the functional clock of the UART. 0h = Smallest value FFFFh = Highest possible value |
LINCTL is shown in Figure 19-53 and described in Table 19-51.
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UART LIN Mode Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINC0_MATCH | LINC1CAP | LINC0CAP | RESERVED | CNTRXLOW | ZERONE | CTRENA |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | 0h | |
6 | LINC0_MATCH | R/W | 0h | Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled. 0h = Counter compare match mode disabled (capture mode enabled) 1h = Counter compare match enabled (capture mode disabled) |
5 | LINC1CAP | R/W | 0h | Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled. 0h = Capture counter on positive UARTxRXD edge disabled 1h = Capture counter on positive UARTxRXD edge enabled |
4 | LINC0CAP | R/W | 0h | Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled. 0h = Capture counter on negative UARTxRXD edge disabled 1h = Capture counter on negative UARTxRXD edge enabled |
3 | RESERVED | R/W | 0h | |
2 | CNTRXLOW | R/W | 0h | Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments. 0h = Count while low Signal on UARTxRXD disabled 1h = Count while low Signal on UARTxRXD enabled |
1 | ZERONE | R/W | 0h | Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD 0h = Zero on negative edge disabled 1h = Zero on negative edge enabled |
0 | CTRENA | R/W | 0h | LIN Counter Enable. LIN counter will only count when enabled. 0h = Counter disabled 1h = Counter enabled |
LINC0 is shown in Figure 19-54 and described in Table 19-52.
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UART LIN Mode Capture 0 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | DATA | R/W | 0h | 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge and can generate a LINC0 interrupt when capture is enabled (LINC0CAP = 1). If compare mode is enabled (LINC0_MATCH = 1), a counter match can generate a LINC0 interrupt. 0h = Smallest value FFFFh = Highest possible value |
LINC1 is shown in Figure 19-55 and described in Table 19-53.
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UART LIN Mode Capture 1 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | DATA | R/W | 0h | 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge and can generate a LINC1 interrupt when capture is enabled (LINC1CAP = 1) 0h = Smallest value FFFFh = Highest possible value |
IRCTL is shown in Figure 19-56 and described in Table 19-54.
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IrDA Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | IRRXPL | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IRTXPL | IRTXCLK | IREN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | 0h | |
9 | IRRXPL | R/W | 0h | IrDA receive input UCAxRXD polarity 0h = HIGH : IrDA transceiver delivers a high pulse when a light pulse is seen 1h = LOW : IrDA transceiver delivers a low pulse when a light pulse is seen |
8 | RESERVED | R/W | 0h | |
7-2 | IRTXPL | R/W | 0h | Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)] (IRTXCLK = functional clock of the UART) 0h = Smallest value 3Fh = Highest possible value |
1 | IRTXCLK | R/W | 0h | IrDA transmit pulse clock select 0h (R/W) = IrDA encode data is based on the functional clock. 1h (R/W) = IrDA encode data is based on the Baud Rate clock< when select 8x oversampling, the IRTXPL cycle should less 8; when select 16x oversampling, the IRTXPL cycle should less 16. |
0 | IREN | R/W | 0h | IrDA encoder/decoder enable 0h (R/W) = IrDA encoder/decoder disabled 1h (R/W) = IrDA encoder/decoder enabled |
AMASK is shown in Figure 19-57 and described in Table 19-55.
Return to the Summary Table.
Self Address Mask Register The AMASK register is used to enable the address mask for 9-bit or Idle-Line mode. The address bits are masked to create a set of addresses to be matched with the
received address byte.
Used in DALI, UART 9-Bit or Idle-Line mode.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | VALUE | R/W | FFh | Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bit field configures, that the corresponding bit in the ADDR bit field of the UARTxADDR register is don't care. A 1 bit in the MSK bit field configures, that the corresponding bit in the ADDR bit field of the UARTxADDR register must match. 0h = Smallest value FFh = Highest possible value |
ADDR is shown in Figure 19-58 and described in Table 19-56.
Return to the Summary Table.
Self Address Register The ADDR register is used to write the specific address that should be matched with the receiving byte when the Address Mask (AMASK) is set to FFh. This register is used in
conjunction with AMASK to form a match for address-byte received.
Used in DALI, UART 9-Bit or Idle-Line mode.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | VALUE | R/W | 0h | Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh. 0h = Smallest value FFh = Highest possible value |
CLKDIV2 is shown in Figure 19-59 and described in Table 19-57.
Return to the Summary Table.
This register is used to specify module-specific divide ratio of the functional clock (only in UART extended).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |