SLAU847D October   2022  – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
    6. 1.6 NONMAIN_L1227_L1228_L2227_L2228 Registers
    7. 1.7 Factory Constants
      1. 1.7.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 RTCCLK (RTC Clock)
        11. 2.3.2.11 External Clock Output (CLK_OUT)
        12. 2.3.2.12 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.5.7 Optimizing for Lowest Wakeup Latency
      8. 2.5.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
    7. 2.7 SYSCTL_L1227_L1228_L2227_L2228 Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 DMA
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 Low Frequency Subsystem (LFSS)
    1. 8.1  Overview
    2. 8.2  Clock System
    3. 8.3  LFSS Reset Using VBAT
    4. 8.4  Power Domains and Supply Detection
      1. 8.4.1 Startup When VBAT Powers on First
      2. 8.4.2 Startup when VDD powers on first
      3. 8.4.3 Behavior When VDD is Lost
      4. 8.4.4 Behavior when VBAT is lost
      5. 8.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 8.4.6 Supercapacitor Charging Circuit
    5. 8.5  Real Time Counter (RTC_x)
    6. 8.6  Independent Watchdog Timer (IWDT)
    7. 8.7  Tamper Input and Output
      1. 8.7.1 IOMUX Mode
      2. 8.7.2 Tamper Mode
        1. 8.7.2.1 Tamper Event Detection
        2. 8.7.2.2 Timestamp Event Output
        3. 8.7.2.3 Heartbeat Generator
        4. 8.7.2.4 RTC Clock Output
    8. 8.8  Scratchpad Memory
    9. 8.9  Lock Function of RTC, TIO, and WDT
    10. 8.10 LFSS Registers
  11. 9 IOMUX
    1. 9.1 IOMUX Overview
      1. 9.1.1 IO Types and Analog Sharing
    2. 9.2 IOMUX Operation
      1. 9.2.1 Peripheral Function (PF) Assignment
      2. 9.2.2 Logic High to Hi-Z Conversion
      3. 9.2.3 Logic Inversion
      4. 9.2.4 SHUTDOWN Mode Wakeup Logic
      5. 9.2.5 Pullup/Pulldown Resistors
      6. 9.2.6 Drive Strength Control
      7. 9.2.7 Hysteresis and Logic Level Control
    3. 9.3 IOMUX (PINCMx) Register Format
    4. 9.4 IOMUX Registers
  12. 10TRNG
    1. 10.1 TRNG Overview
    2. 10.2 TRNG Operation
      1. 10.2.1 TRNG Generation Data Path
      2. 10.2.2 Clock Configuration and Output Rate
      3. 10.2.3 Behavior in Low Power Modes
      4. 10.2.4 Health Tests
        1. 10.2.4.1 Digital Block Startup Self-Test
        2. 10.2.4.2 Analog Block Startup Self-Test
        3. 10.2.4.3 Runtime Health Test
          1. 10.2.4.3.1 Repetition Count Test
          2. 10.2.4.3.2 Adaptive Proportion Test
          3. 10.2.4.3.3 Handling Runtime Health Test Failures
      5. 10.2.5 Configuration
        1. 10.2.5.1 TRNG State Machine
          1. 10.2.5.1.1 Changing TRNG States
        2. 10.2.5.2 Using the TRNG
        3. 10.2.5.3 TRNG Events
          1. 10.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 10.3 TRNG Registers
  13. 11AESADV
    1. 11.1 AESADV Overview
      1. 11.1.1 AESADV Performance
    2. 11.2 AESADV Operation
      1. 11.2.1 Loading the Key
      2. 11.2.2 Writing Input Data
      3. 11.2.3 Reading Output Data
      4. 11.2.4 Operation Descriptions
        1. 11.2.4.1 Single Block Operation
        2. 11.2.4.2 Electronic Codebook (ECB) Mode
          1. 11.2.4.2.1 ECB Encryption
          2. 11.2.4.2.2 ECB Decryption
        3. 11.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 11.2.4.3.1 CBC Encryption
          2. 11.2.4.3.2 CBC Decryption
        4. 11.2.4.4 Output Feedback (OFB) Mode
          1. 11.2.4.4.1 OFB Encryption
          2. 11.2.4.4.2 OFB Decryption
        5. 11.2.4.5 Cipher Feedback (CFB) Mode
          1. 11.2.4.5.1 CFB Encryption
          2. 11.2.4.5.2 CFB Decryption
        6. 11.2.4.6 Counter (CTR) Mode
          1. 11.2.4.6.1 CTR Encryption
          2. 11.2.4.6.2 CTR Decryption
        7. 11.2.4.7 Galois Counter (GCM) Mode
          1. 11.2.4.7.1 GHASH Operation
          2. 11.2.4.7.2 GCM Operating Modes
            1. 11.2.4.7.2.1 Autonomous GCM Operation
              1. 11.2.4.7.2.1.1 GMAC
            2. 11.2.4.7.2.2 GCM With Pre-Calculations
            3. 11.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 11.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 11.2.4.8.1 CCM Operation
      5. 11.2.5 AES Events
        1. 11.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 11.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 11.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 11.3 AESADV Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13GPIO
    1. 13.1 GPIO Overview
    2. 13.2 GPIO Operation
      1. 13.2.1 GPIO Ports
      2. 13.2.2 GPIO Read/Write Interface
      3. 13.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 13.2.4 GPIO Fast Wake
      5. 13.2.5 GPIO DMA Interface
      6. 13.2.6 Event Publishers and Subscribers
    3. 13.3 GPIO Registers
  16. 14ADC
    1. 14.1 ADC Overview
    2. 14.2 ADC Operation
      1. 14.2.1  ADC Core
      2. 14.2.2  Voltage Reference Options
      3. 14.2.3  Generic Resolution Modes
      4. 14.2.4  Hardware Averaging
      5. 14.2.5  ADC Clocking
      6. 14.2.6  Common ADC Use Cases
      7. 14.2.7  Power Down Behavior
      8. 14.2.8  Sampling Trigger Sources and Sampling Modes
        1. 14.2.8.1 AUTO Sampling Mode
        2. 14.2.8.2 MANUAL Sampling Mode
      9. 14.2.9  Sampling Period
      10. 14.2.10 Conversion Modes
      11. 14.2.11 Data Format
      12. 14.2.12 Advanced Features
        1. 14.2.12.1 Window Comparator
        2. 14.2.12.2 DMA and FIFO Operation
        3. 14.2.12.3 Analog Peripheral Interconnection
      13. 14.2.13 Status Register
      14. 14.2.14 ADC Events
        1. 14.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 14.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 ADC12 Registers
  17. 15COMP
    1. 15.1 Comparator Overview
    2. 15.2 Comparator Operation
      1. 15.2.1  Comparator Configuration
      2. 15.2.2  Comparator Channels Selection
      3. 15.2.3  Comparator Output
      4. 15.2.4  Output Filter
      5. 15.2.5  Sampled Output Mode
      6. 15.2.6  Blanking Mode
      7. 15.2.7  Reference Voltage Generator
      8. 15.2.8  Comparator Hysteresis
      9. 15.2.9  Input SHORT Switch
      10. 15.2.10 Interrupt and Events Support
        1. 15.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.10.3 Generic Event Subscribers
    3. 15.3 COMP Registers
  18. 16OPA
    1. 16.1 OPA Overview
    2. 16.2 OPA Operation
      1. 16.2.1 Analog Core
      2. 16.2.2 Power Up Behavior
      3. 16.2.3 Inputs
      4. 16.2.4 Output
      5. 16.2.5 Clock Requirements
      6. 16.2.6 Chopping
      7. 16.2.7 OPA Amplifier Modes
        1. 16.2.7.1 General-Purpose Mode
        2. 16.2.7.2 Buffer Mode
        3. 16.2.7.3 OPA PGA Mode
          1. 16.2.7.3.1 Inverting PGA Mode
          2. 16.2.7.3.2 Non-inverting PGA Mode
        4. 16.2.7.4 Difference Amplifier Mode
        5. 16.2.7.5 Cascade Amplifier Mode
      8. 16.2.8 OPA Configuration Selection
      9. 16.2.9 Burnout Current Source
    3. 16.3 OA Registers
  19. 17GPAMP
    1. 17.1 GPAMP Overview
    2. 17.2 GPAMP Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 GPAMP Amplifier Modes
        1. 17.2.5.1 General-Purpose Mode
        2. 17.2.5.2 ADC Buffer Mode
        3. 17.2.5.3 Unity Gain Mode
      6. 17.2.6 Chopping
    3. 17.3 GPAMP Registers
  20. 18VREF
    1. 18.1 VREF Overview
    2. 18.2 VREF Operation
      1. 18.2.1 Internal Reference Generation
      2. 18.2.2 External Reference Input
      3. 18.2.3 Analog Peripheral Interface
    3. 18.3 VREF Registers
  21. 19UART
    1. 19.1 UART Overview
      1. 19.1.1 Purpose of the Peripheral
      2. 19.1.2 Features
      3. 19.1.3 Functional Block Diagram
    2. 19.2 UART Operation
      1. 19.2.1 Clock Control
      2. 19.2.2 Signal Descriptions
      3. 19.2.3 General Architecture and Protocol
        1. 19.2.3.1  Transmit Receive Logic
        2. 19.2.3.2  Bit Sampling
        3. 19.2.3.3  Majority Voting Feature
        4. 19.2.3.4  Baud Rate Generation
        5. 19.2.3.5  Data Transmission
        6. 19.2.3.6  Error and Status
        7. 19.2.3.7  Local Interconnect Network (LIN) Support
          1. 19.2.3.7.1 LIN Responder Transmission Delay
        8. 19.2.3.8  Flow Control
        9. 19.2.3.9  Idle-Line Multiprocessor
        10. 19.2.3.10 9-Bit UART Mode
        11. 19.2.3.11 RS485 Support
        12. 19.2.3.12 DALI Protocol
        13. 19.2.3.13 Manchester Encoding and Decoding
        14. 19.2.3.14 IrDA Encoding and Decoding
        15. 19.2.3.15 ISO7816 Smart Card Support
        16. 19.2.3.16 Address Detection
        17. 19.2.3.17 FIFO Operation
        18. 19.2.3.18 Loopback Operation
        19. 19.2.3.19 Glitch Suppression
      4. 19.2.4 Low Power Operation
      5. 19.2.5 Reset Considerations
      6. 19.2.6 Initialization
      7. 19.2.7 Interrupt and Events Support
        1. 19.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 19.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 19.2.8 Emulation Modes
    3. 19.3 UART Registers
  22. 20SPI
    1. 20.1 SPI Overview
      1. 20.1.1 Purpose of the Peripheral
      2. 20.1.2 Features
      3. 20.1.3 Functional Block Diagram
      4. 20.1.4 External Connections and Signal Descriptions
    2. 20.2 SPI Operation
      1. 20.2.1 Clock Control
      2. 20.2.2 General Architecture
        1. 20.2.2.1 Chip Select and Command Handling
          1. 20.2.2.1.1 Chip Select Control
          2. 20.2.2.1.2 Command Data Control
        2. 20.2.2.2 Data Format
        3. 20.2.2.3 Delayed data sampling
        4. 20.2.2.4 Clock Generation
        5. 20.2.2.5 FIFO Operation
        6. 20.2.2.6 Loopback mode
        7. 20.2.2.7 DMA Operation
        8. 20.2.2.8 Repeat Transfer mode
        9. 20.2.2.9 Low Power Mode
      3. 20.2.3 Protocol Descriptions
        1. 20.2.3.1 Motorola SPI Frame Format
        2. 20.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 20.2.4 Reset Considerations
      5. 20.2.5 Initialization
      6. 20.2.6 Interrupt and Events Support
        1. 20.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 20.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 20.2.7 Emulation Modes
    3. 20.3 SPI Registers
  23. 21I2C
    1. 21.1 I2C Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
      4. 21.1.4 Environment and External Connections
    2. 21.2 I2C Operation
      1. 21.2.1 Clock Control
        1. 21.2.1.1 Clock Select and I2C Speed
        2. 21.2.1.2 Clock Startup
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture
        1. 21.2.3.1  I2C Bus Functional Overview
        2. 21.2.3.2  START and STOP Conditions
        3. 21.2.3.3  Data Format with 7-Bit Address
        4. 21.2.3.4  Acknowledge
        5. 21.2.3.5  Repeated Start
        6. 21.2.3.6  SCL Clock Low Timeout
        7. 21.2.3.7  Clock Stretching
        8. 21.2.3.8  Dual Address
        9. 21.2.3.9  Arbitration
        10. 21.2.3.10 Multiple Controller Mode
        11. 21.2.3.11 Glitch Suppression
        12. 21.2.3.12 FIFO operation
          1. 21.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 21.2.3.13 Loopback mode
        14. 21.2.3.14 Burst Mode
        15. 21.2.3.15 DMA Operation
        16. 21.2.3.16 Low-Power Operation
      4. 21.2.4 Protocol Descriptions
        1. 21.2.4.1 I2C Controller Mode
          1. 21.2.4.1.1 Controller Configuration
          2. 21.2.4.1.2 Controller Mode Operation
          3. 21.2.4.1.3 Read On TX Empty
        2. 21.2.4.2 I2C Target Mode
          1. 21.2.4.2.1 Target Mode Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 21.2.8 Emulation Modes
    3. 21.3 I2C Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23Timers (TIMx)
    1. 23.1 TIMx Overview
      1. 23.1.1 TIMG Overview
        1. 23.1.1.1 TIMG Features
        2. 23.1.1.2 Functional Block Diagram
      2. 23.1.2 TIMA Overview
        1. 23.1.2.1 TIMA Features
        2. 23.1.2.2 Functional Block Diagram
      3. 23.1.3 TIMx Instance Configuration
    2. 23.2 TIMx Operation
      1. 23.2.1  Timer Counter
        1. 23.2.1.1 Clock Source Select and Prescaler
          1. 23.2.1.1.1 Internal Clock and Prescaler
          2. 23.2.1.1.2 External Signal Trigger
        2. 23.2.1.2 Repeat Counter (TIMA only)
      2. 23.2.2  Counting Mode Control
        1. 23.2.2.1 One-shot and Periodic Modes
        2. 23.2.2.2 Down Counting Mode
        3. 23.2.2.3 Up/Down Counting Mode
        4. 23.2.2.4 Up Counting Mode
        5. 23.2.2.5 Phase Load (TIMA only)
      3. 23.2.3  Capture/Compare Module
        1. 23.2.3.1 Capture Mode
          1. 23.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 23.2.3.1.1.1 CCP Input Edge Synchronization
            2. 23.2.3.1.1.2 CCP Input Pulse Conditions
            3. 23.2.3.1.1.3 Counter Control Operation
            4. 23.2.3.1.1.4 CCP Input Filtering
            5. 23.2.3.1.1.5 Input Selection
          2. 23.2.3.1.2 Use Cases
            1. 23.2.3.1.2.1 Edge Time Capture
            2. 23.2.3.1.2.2 Period Capture
            3. 23.2.3.1.2.3 Pulse Width Capture
            4. 23.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 23.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 23.2.3.1.3.1 QEI With 2-Signal
            2. 23.2.3.1.3.2 QEI With Index Input
            3. 23.2.3.1.3.3 QEI Error Detection
          4. 23.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 23.2.3.2 Compare Mode
          1. 23.2.3.2.1 Edge Count
      4. 23.2.4  Shadow Load and Shadow Compare
        1. 23.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 23.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 23.2.5  Output Generator
        1. 23.2.5.1 Configuration
        2. 23.2.5.2 Use Cases
          1. 23.2.5.2.1 Edge-Aligned PWM
          2. 23.2.5.2.2 Center-Aligned PWM
          3. 23.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 23.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 23.2.5.3 Forced Output
      6. 23.2.6  Fault Handler (TIMA only)
        1. 23.2.6.1 Fault Input Conditioning
        2. 23.2.6.2 Fault Input Sources
        3. 23.2.6.3 Counter Behavior With Fault Conditions
        4. 23.2.6.4 Output Behavior With Fault Conditions
      7. 23.2.7  Synchronization With Cross Trigger
        1. 23.2.7.1 Main Timer Cross Trigger Configuration
        2. 23.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 23.2.8  Low Power Operation
      9. 23.2.9  Interrupt and Event Support
        1. 23.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 23.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 23.2.10 Debug Handler (TIMA Only)
    3. 23.3 TIMx Registers
  26. 24LCD
    1. 24.1 LCD Introduction
      1. 24.1.1 LCD Operating Principle
      2. 24.1.2 LCD Mux Modes
      3. 24.1.3 Introduction
      4. 24.1.4 LCD Waveforms
    2. 24.2 LCD Clocking
    3. 24.3 Voltage Generation
      1. 24.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 24.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 24.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 24.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 24.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 24.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 24.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 24.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 24.3.9  Charge pump
      10. 24.3.10 Internal Reference Generation
    4. 24.4 Analog Mux
      1. 24.4.1 Static Mode
      2. 24.4.2 Non-Static 1/3 bias mode
      3. 24.4.3 Non-Static 1/4 bias mode
      4. 24.4.4 Low power mode switch controls
    5. 24.5 LCD Memory and output drive
      1. 24.5.1 LCD Memory organization
        1. 24.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 24.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 24.5.1.3 Configuring memory
        4. 24.5.1.4 Accessing memory and output drive
        5. 24.5.1.5 Blinking Override
    6. 24.6 IO Muxing
    7. 24.7 Interrupt Generation
    8. 24.8 Power Domains and Power Modes
    9. 24.9 LCD Registers
  27. 25RTC
    1. 25.1 Overview
      1. 25.1.1 RTC Instances
    2. 25.2 Basic Operation
    3. 25.3 Configuration
      1. 25.3.1  Clocking
      2. 25.3.2  Reading and Writing to RTC Peripheral Registers
      3. 25.3.3  Binary vs. BCD
      4. 25.3.4  Leap Year Handling
      5. 25.3.5  Calendar Alarm Configuration
      6. 25.3.6  Interval Alarm Configuration
      7. 25.3.7  Periodic Alarm Configuration
      8. 25.3.8  Calibration
        1. 25.3.8.1 Crystal Offset Error
          1. 25.3.8.1.1 Offset Error Correction Mechanism
        2. 25.3.8.2 Crystal Temperature Error
          1. 25.3.8.2.1 Temperature Drift Correction Mechanism
      9. 25.3.9  RTC Prescaler Extension
      10. 25.3.10 RTC Timestamp Capture
      11. 25.3.11 RTC Events
        1. 25.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 25.4 RTC Registers
  28. 26IWDT
    1. 26.1 IWDT Initialization after LFSS Reset
    2. 26.2 IWDT Clock Configuration
    3. 26.3 IWDT Period Selection
    4. 26.4 Debug Behavior of the IWDT
    5. 26.5 IWDT Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

1.5 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers

Table 1-6 lists the memory-mapped registers for the NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 registers. All register offset addresses not listed in Table 1-6 should be considered as reserved locations and the register contents should not be modified.

Table 1-6 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
OffsetAcronymRegister NameSection
41C00000hBCRCONFIGIDConfiguration ID of BCR StructureSection 1.5.1
41C00004hBOOTCFG0Serial wire debug (SWD) lock policy.Section 1.5.2
41C00008hBOOTCFG1BSL invoke pin policy.Section 1.5.3
41C0000Ch + formulaPWDDEBUGLOCK_ySWD command and password authentication request.Section 1.5.4
41C0001ChBOOTCFG2Fast boot mode policy and BSL mode policy.Section 1.5.5
41C00020hBOOTCFG3Mass erase and factory reset mode policies.Section 1.5.6
41C00024h + formulaPWDMASSERASE_ySWD Mass Erase request and data exchangeSection 1.5.7
41C00034h + formulaPWDFACTORYRESET_ySWD Factory Reset request and data exchange.Section 1.5.8
41C00044hSWPMAINLOWPrograms Static write protection of first 32K bytes.Section 1.5.9
41C00048hSWPMAINHIGHPrograms Static write protection of first 32K bytes.Section 1.5.10
41C0004ChBOOTCFG4Section 1.5.11
41C00050hAPPCRCSTARTStart address of the application CRC check (must be an address in a MAIN flash region).Section 1.5.12
41C00054hAPPCRCLENGTHLength of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.Section 1.5.13
41C00058hAPPCRCExpected application CRC check digest (CRC-32) to test against during boot.Section 1.5.14
41C0005ChBOOTCRCCRC digest (CRC-32) of the BCR configuration portion of the NONMAIN memory.Section 1.5.15
41C00100hBSLIDBSL configuration ID.Section 1.5.16
41C00104hBSLPINCFG0BSL UART PIN Configuration.Section 1.5.17
41C00108hBSLPINCFG1BSL I2C PIN Configuration.Section 1.5.18
41C0010ChBSLCONFIG0BSL invoke pin configuration and memory read-out policy.Section 1.5.19
41C00110h + formulaBSLPW_y256-bit BSL access password.Section 1.5.20
41C00130hBSLPLUGINCFGDefines the presence and type of a BSL plug-in in MAIN flash memory.Section 1.5.21
41C00134h + formulaBSLPLUGINHOOK_yFunction pointers for plug-in init, receive, transmit, and de-init functions.Section 1.5.22
41C00144hPATCHHOOKIDAlternate BSL configuration.Section 1.5.23
41C00148hSBLADDRESSAddress of an alternate BSL.Section 1.5.24
41C0014ChBSLAPPVERAddress of the application version word.Section 1.5.25
41C00150hBSLSECCFGBSL security configuration.Section 1.5.26
41C00154hBSLCRCCRC digest (CRC-32) of the BSL_CONFIG portion of the NONMAIN memory.Section 1.5.27

Complex bit access types are encoded to fit into small table cells. Table 1-7 shows the codes that are used for access types in this section.

Table 1-7 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

1.5.1 BCRCONFIGID Register (Offset = 41C00000h) [Reset = 00000000h]

BCRCONFIGID is shown in Table 1-8.

Return to the Summary Table.

Configuration ID of BCR Structure

Table 1-8 BCRCONFIGID Register Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W0hConfiguration ID of the BOOTCFG

1.5.2 BOOTCFG0 Register (Offset = 41C00004h) [Reset = 00000000h]

BOOTCFG0 is shown in Table 1-9.

Return to the Summary Table.

Serial wire debug (SWD) lock policy.

Table 1-9 BOOTCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-16SWDP_MODER/W0hUsed to enable/ disable SWD port access.
AABBh = Enabled;
FFFFh = Disabled (all other values).
15-0SWDLOCKPOLICYW0hThe serial wire debug (SWD) lockout may be configured to one of three policies: no restrictions, core debug access requires a password match, and maximally restrictive.
AABBh = Access to all debug APs via SWD is enabled;
CCDDh = AHB-AP, ET-AP, and PWR-AP access via SWD is only enabled with a password match.
FFFFh = SWD access is completely disabled (all other values);

1.5.3 BOOTCFG1 Register (Offset = 41C00008h) [Reset = 00000000h]

BOOTCFG1 is shown in Table 1-10.

Return to the Summary Table.

BSL invoke pin policy.

Table 1-10 BOOTCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-16BSL_PIN_INVOKER/W0hIf enabled, execute GPIO based BSL invocation check, else not executed.
AABBh = Enabled;
FFFFh = Disabled (all other values).
15-0TI_FA_MODER/W0hIf enabled, re-test request through DSSM is serviced, else not serviced.
AABBh = Enabled;
FFFFh = Disabled (all other values).

1.5.4 PWDDEBUGLOCK_y Register (Offset = 41C0000Ch + formula) [Reset = 00000000h]

PWDDEBUGLOCK_y is shown in Table 1-11.

Return to the Summary Table.

SWD command and password authentication request.

Offset = 41C0000Ch + (y * 4h); where y = 0h to 3h

Table 1-11 PWDDEBUGLOCK_y Register Field Descriptions
BitFieldTypeResetDescription
31-0PWR/W0hPassword

1.5.5 BOOTCFG2 Register (Offset = 41C0001Ch) [Reset = 00000000h]

BOOTCFG2 is shown in Table 1-12.

Return to the Summary Table.

Fast boot mode policy and BSL mode policy.

Table 1-12 BOOTCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-16BSLMODER/W0hEnable or disable the BSL.
AABBh = The BSL is enabled
FFFFh = The BSL is disabled.
15-0FASTBOOTMODER/W0hEnable or disable the fast boot mode.
AABBh = Fast boot mode is enabled. Only the software BSL invoke condition is evaluated.
FFFFh = Fast boot mode is disabled. All enabled BSL invoke conditions are evaluated.

1.5.6 BOOTCFG3 Register (Offset = 41C00020h) [Reset = 00000000h]

BOOTCFG3 is shown in Table 1-13.

Return to the Summary Table.

Mass erase and factory reset mode policies.

Table 1-13 BOOTCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-16factoryResetModeR/W0h
AABBh = Enabled;
CCDDh = Enabled with password;
FFFFh = Disabled (all other values).
15-0massEraseModeR/W0h
AABBh = Enabled;
CCDDh = Enabled with password;
FFFFh = Disabled (all other values).

1.5.7 PWDMASSERASE_y Register (Offset = 41C00024h + formula) [Reset = 00000000h]

PWDMASSERASE_y is shown in Table 1-14.

Return to the Summary Table.

SWD Mass Erase request and data exchange

Offset = 41C00024h + (y * 4h); where y = 0h to 3h

Table 1-14 PWDMASSERASE_y Register Field Descriptions
BitFieldTypeResetDescription
31-0PWR/W0hPassword

1.5.8 PWDFACTORYRESET_y Register (Offset = 41C00034h + formula) [Reset = 00000000h]

PWDFACTORYRESET_y is shown in Table 1-15.

Return to the Summary Table.

SWD Factory Reset request and data exchange.

Offset = 41C00034h + (y * 4h); where y = 0h to 3h

Table 1-15 PWDFACTORYRESET_y Register Field Descriptions
BitFieldTypeResetDescription
31-0PWR/W0hPassword

1.5.9 SWPMAINLOW Register (Offset = 41C00044h) [Reset = 00000000h]

SWPMAINLOW is shown in Table 1-16.

Return to the Summary Table.

Programs Static write protection of first 32K bytes.

Table 1-16 SWPMAINLOW Register Field Descriptions
BitFieldTypeResetDescription
31-0MAINLOWR/W0h1 bit per sector (Setting a bit to 0 disables write, 1 enables write).

1.5.10 SWPMAINHIGH Register (Offset = 41C00048h) [Reset = 00000000h]

SWPMAINHIGH is shown in Table 1-17.

Return to the Summary Table.

Programs Static write protection of first 32K bytes.

Table 1-17 SWPMAINHIGH Register Field Descriptions
BitFieldTypeResetDescription
31-0MAINHIGHR/W0h1 bit per 8 sectors. Bits 3:0, not used as covered with above.(Setting a bit to 0 disables write, 1 enables write)

1.5.11 BOOTCFG4 Register (Offset = 41C0004Ch) [Reset = 00000000h]

BOOTCFG4 is shown in Table 1-18.

Return to the Summary Table.

Table 1-18 BOOTCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-16APPCRCMODER/W0hAPPCRCMODE enables or disables the boot time CRC check of a segment of MAIN flash memory.
AABBh = The boot time MAIN flash CRC check is enabled. If the boot time CRC check passes, the application code in MAIN flash is started unless the reset vector or stack pointer are blank (unprogrammed). In the event of a failing CRC check, the application code in MAIN flash will not be started and the boot process fails.
FFFFh = The boot time MAIN flash CRC check is disabled. The application code in MAIN flash is always started unless the reset vector or stack pointer are blank (unprogrammed).
15-0SWPNONMAINR/W0hStatic Write Protection configuration for Non-Main. Only one LSB used (Setting bit to 0 disables write, 1 enables write).

1.5.12 APPCRCSTART Register (Offset = 41C00050h) [Reset = 00000000h]

APPCRCSTART is shown in Table 1-19.

Return to the Summary Table.

Start address of the application CRC check (must be an address in a MAIN flash region).

Table 1-19 APPCRCSTART Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hApplication CRC check start address

1.5.13 APPCRCLENGTH Register (Offset = 41C00054h) [Reset = 00000000h]

APPCRCLENGTH is shown in Table 1-20.

Return to the Summary Table.

Length of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.

Table 1-20 APPCRCLENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0LENGTHR/W0hApplication CRC check source data length

1.5.14 APPCRC Register (Offset = 41C00058h) [Reset = 00000000h]

APPCRC is shown in Table 1-21.

Return to the Summary Table.

Expected application CRC check digest (CRC-32) to test against during boot.

Table 1-21 APPCRC Register Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W0hApplication CRC check digest

1.5.15 BOOTCRC Register (Offset = 41C0005Ch) [Reset = 00000000h]

BOOTCRC is shown in Table 1-22.

Return to the Summary Table.

CRC digest (CRC-32) of the BCR configuration portion of the NONMAIN memory.

Table 1-22 BOOTCRC Register Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W0hBCR configuration data CRC digest

1.5.16 BSLID Register (Offset = 41C00100h) [Reset = 00000000h]

BSLID is shown in Table 1-23.

Return to the Summary Table.

BSL configuration ID.

Table 1-23 BSLID Register Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W0hConfiguration ID of the BOOTCFG

1.5.17 BSLPINCFG0 Register (Offset = 41C00104h) [Reset = 00000000h]

BSLPINCFG0 is shown in Table 1-24.

Return to the Summary Table.

BSL UART PIN Configuration.

Table 1-24 BSLPINCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-24UARTTX_MUX_SELR/W0hUART TX PIN FUNCTION Mux selection
23-16UARTTX_PAD_NUMR/W0hUART TX Pad Number
15-8UARTRX_MUX_SELR/W0hUART RX PIN FUNCTION Mux selection
7-0UARTRX_PAD_NUMR/W0hUART RX Pad Number

1.5.18 BSLPINCFG1 Register (Offset = 41C00108h) [Reset = 00000000h]

BSLPINCFG1 is shown in Table 1-25.

Return to the Summary Table.

BSL I2C PIN Configuration.

Table 1-25 BSLPINCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-24I2CSCL_MUX_SELR/W0hI2C SCL PIN FUNCTION Mux selection
23-16I2CSCL_PAD_NUMR/W0hI2C SCL Pad Number
15-8I2CSDA_MUX_SELR/W0hI2C SDA PIN FUNCTION Mux selection
7-0I2CSDA_PAD_NUMR/W0hI2C SDA Pad Number

1.5.19 BSLCONFIG0 Register (Offset = 41C0010Ch) [Reset = 00000000h]

BSLCONFIG0 is shown in Table 1-26.

Return to the Summary Table.

BSL invoke pin configuration and memory read-out policy.

Table 1-26 BSLCONFIG0 Register Field Descriptions
BitFieldTypeResetDescription
31-16READOUTENR/W0hSets the memory read-out policy for the BSL interface.
AABBh = Memory contents may be read via the BSL interface.
FFFFh = Memory read-out is not possible via the BSL interface.
15-14RESERVEDR0h
13BSLIVK_GPIOPORTR/W0hThe BSL_invoke GPIO port index corresponding to the pad used for BSL_invoke.
0h = The BSL_invoke pin is on GPIO port A.
1h = The BSL_invoke pin is on GPIO port B.
12-8BSLIVK_GPIOPINR/W0hThe BSL_invoke GPIO pin index corresponding to the pad used for BSL_invoke.
7BSLIVK_LVLR/W0hThe BSL_invoke input logic level which shall invoke the BSL.
0h = LOW
1h = HIGH
6RESERVEDR0h
5-0BSLIVK_PINCMR/W0hThe IOMUX PINCMx register index corresponding to the pad to be used for BSL_invoke.

1.5.20 BSLPW_y Register (Offset = 41C00110h + formula) [Reset = 00000000h]

BSLPW_y is shown in Table 1-27.

Return to the Summary Table.

256-bit BSL access password.

Offset = 41C00110h + (y * 4h); where y = 0h to 7h

Table 1-27 BSLPW_y Register Field Descriptions
BitFieldTypeResetDescription
31-0PWR/W0hPW

1.5.21 BSLPLUGINCFG Register (Offset = 41C00130h) [Reset = 00000000h]

BSLPLUGINCFG is shown in Table 1-28.

Return to the Summary Table.

Defines the presence and type of a BSL plug-in in MAIN flash memory.

Table 1-28 BSLPLUGINCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24SRAMEXISTSR/W0hSRAM consumed by Flash plugin, from 0x00 to 0xFF.
23-16FLASHEXISTSR/W0hThe field tells if Flash Plugin exists are not. 0xBB - Flash Plugin exists; 0xFF (all other values) - Only ROM plugins will be used.
15-0PLUGINTYPER/W0hThe type code for the BSL plug-in.
1000h = Plug-in is for UART.
2000h = Plug-in is for I2C.
FFFFh = For all other values. Any other interfaces with valid hooks will be added to Plugin list.

1.5.22 BSLPLUGINHOOK_y Register (Offset = 41C00134h + formula) [Reset = 00000000h]

BSLPLUGINHOOK_y is shown in Table 1-29.

Return to the Summary Table.

Function pointers for plug-in init, receive, transmit, and de-init functions.

Offset = 41C00134h + (y * 4h); where y = 0h to 3h

Table 1-29 BSLPLUGINHOOK_y Register Field Descriptions
BitFieldTypeResetDescription
31-0BSLPLUGINR/W0hAddress of the BSL plug-in hook. Byte [3-0] : Init; Byte [7-4] : Receive; Byte [11-8] : Send; Byte [15-12] : Deinit

1.5.23 PATCHHOOKID Register (Offset = 41C00144h) [Reset = 00000000h]

PATCHHOOKID is shown in Table 1-30.

Return to the Summary Table.

Alternate BSL configuration.

Table 1-30 PATCHHOOKID Register Field Descriptions
BitFieldTypeResetDescription
31-0IDR/W0hID field to invoke an alternate BSL.
AAAAAAAAh = Use the alternate BSL.
FFFFFFFFh = Do not use an alternate BSL.

1.5.24 SBLADDRESS Register (Offset = 41C00148h) [Reset = 00000000h]

SBLADDRESS is shown in Table 1-31.

Return to the Summary Table.

Address of an alternate BSL.

Table 1-31 SBLADDRESS Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hAddress of the alternate BSL, if present.

1.5.25 BSLAPPVER Register (Offset = 41C0014Ch) [Reset = 00000000h]

BSLAPPVER is shown in Table 1-32.

Return to the Summary Table.

Address of the application version word.

Table 1-32 BSLAPPVER Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/W0hAddress of the application version word (must be a valid flash address to be returned).

1.5.26 BSLSECCFG Register (Offset = 41C00150h) [Reset = 00000000h]

BSLSECCFG is shown in Table 1-33.

Return to the Summary Table.

BSL security configuration.

Table 1-33 BSLSECCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16TARGETADDRR/W0hI2C target address to be used for the BSL I2C communication.
15-0ALERTACTIONR/W0hAction to take upon a security alert condition.
AABBh = Trigger a factory reset. Note that if sectors in MAIN or NONMAIN flash are write protected they will not be affected by the BSL factory reset.
CCDDh = Re-configure the NONMAIN region to disable the BSL. This is not supported if the NONMAIN region is configured to be write protected.
FFFFh = Ignore the security alert condition (all other values).

1.5.27 BSLCRC Register (Offset = 41C00154h) [Reset = 00000000h]

BSLCRC is shown in Table 1-34.

Return to the Summary Table.

CRC digest (CRC-32) of the BSL_CONFIG portion of the NONMAIN memory.

Table 1-34 BSLCRC Register Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W0hBSL configuration data CRC digest