SLAU847D October   2022  – May 2024 MSPM0L1105 , MSPM0L1106 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
    6. 1.6 NONMAIN_L1227_L1228_L2227_L2228 Registers
    7. 1.7 Factory Constants
      1. 1.7.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 RTCCLK (RTC Clock)
        11. 2.3.2.11 External Clock Output (CLK_OUT)
        12. 2.3.2.12 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.5.7 Optimizing for Lowest Wakeup Latency
      8. 2.5.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
    7. 2.7 SYSCTL_L1227_L1228_L2227_L2228 Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 DMA
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 Low Frequency Subsystem (LFSS)
    1. 8.1  Overview
    2. 8.2  Clock System
    3. 8.3  LFSS Reset Using VBAT
    4. 8.4  Power Domains and Supply Detection
      1. 8.4.1 Startup When VBAT Powers on First
      2. 8.4.2 Startup when VDD powers on first
      3. 8.4.3 Behavior When VDD is Lost
      4. 8.4.4 Behavior when VBAT is lost
      5. 8.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 8.4.6 Supercapacitor Charging Circuit
    5. 8.5  Real Time Counter (RTC_x)
    6. 8.6  Independent Watchdog Timer (IWDT)
    7. 8.7  Tamper Input and Output
      1. 8.7.1 IOMUX Mode
      2. 8.7.2 Tamper Mode
        1. 8.7.2.1 Tamper Event Detection
        2. 8.7.2.2 Timestamp Event Output
        3. 8.7.2.3 Heartbeat Generator
        4. 8.7.2.4 RTC Clock Output
    8. 8.8  Scratchpad Memory
    9. 8.9  Lock Function of RTC, TIO, and WDT
    10. 8.10 LFSS Registers
  11. 9 IOMUX
    1. 9.1 IOMUX Overview
      1. 9.1.1 IO Types and Analog Sharing
    2. 9.2 IOMUX Operation
      1. 9.2.1 Peripheral Function (PF) Assignment
      2. 9.2.2 Logic High to Hi-Z Conversion
      3. 9.2.3 Logic Inversion
      4. 9.2.4 SHUTDOWN Mode Wakeup Logic
      5. 9.2.5 Pullup/Pulldown Resistors
      6. 9.2.6 Drive Strength Control
      7. 9.2.7 Hysteresis and Logic Level Control
    3. 9.3 IOMUX (PINCMx) Register Format
    4. 9.4 IOMUX Registers
  12. 10TRNG
    1. 10.1 TRNG Overview
    2. 10.2 TRNG Operation
      1. 10.2.1 TRNG Generation Data Path
      2. 10.2.2 Clock Configuration and Output Rate
      3. 10.2.3 Behavior in Low Power Modes
      4. 10.2.4 Health Tests
        1. 10.2.4.1 Digital Block Startup Self-Test
        2. 10.2.4.2 Analog Block Startup Self-Test
        3. 10.2.4.3 Runtime Health Test
          1. 10.2.4.3.1 Repetition Count Test
          2. 10.2.4.3.2 Adaptive Proportion Test
          3. 10.2.4.3.3 Handling Runtime Health Test Failures
      5. 10.2.5 Configuration
        1. 10.2.5.1 TRNG State Machine
          1. 10.2.5.1.1 Changing TRNG States
        2. 10.2.5.2 Using the TRNG
        3. 10.2.5.3 TRNG Events
          1. 10.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 10.3 TRNG Registers
  13. 11AESADV
    1. 11.1 AESADV Overview
      1. 11.1.1 AESADV Performance
    2. 11.2 AESADV Operation
      1. 11.2.1 Loading the Key
      2. 11.2.2 Writing Input Data
      3. 11.2.3 Reading Output Data
      4. 11.2.4 Operation Descriptions
        1. 11.2.4.1 Single Block Operation
        2. 11.2.4.2 Electronic Codebook (ECB) Mode
          1. 11.2.4.2.1 ECB Encryption
          2. 11.2.4.2.2 ECB Decryption
        3. 11.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 11.2.4.3.1 CBC Encryption
          2. 11.2.4.3.2 CBC Decryption
        4. 11.2.4.4 Output Feedback (OFB) Mode
          1. 11.2.4.4.1 OFB Encryption
          2. 11.2.4.4.2 OFB Decryption
        5. 11.2.4.5 Cipher Feedback (CFB) Mode
          1. 11.2.4.5.1 CFB Encryption
          2. 11.2.4.5.2 CFB Decryption
        6. 11.2.4.6 Counter (CTR) Mode
          1. 11.2.4.6.1 CTR Encryption
          2. 11.2.4.6.2 CTR Decryption
        7. 11.2.4.7 Galois Counter (GCM) Mode
          1. 11.2.4.7.1 GHASH Operation
          2. 11.2.4.7.2 GCM Operating Modes
            1. 11.2.4.7.2.1 Autonomous GCM Operation
              1. 11.2.4.7.2.1.1 GMAC
            2. 11.2.4.7.2.2 GCM With Pre-Calculations
            3. 11.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 11.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 11.2.4.8.1 CCM Operation
      5. 11.2.5 AES Events
        1. 11.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 11.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 11.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 11.3 AESADV Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13GPIO
    1. 13.1 GPIO Overview
    2. 13.2 GPIO Operation
      1. 13.2.1 GPIO Ports
      2. 13.2.2 GPIO Read/Write Interface
      3. 13.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 13.2.4 GPIO Fast Wake
      5. 13.2.5 GPIO DMA Interface
      6. 13.2.6 Event Publishers and Subscribers
    3. 13.3 GPIO Registers
  16. 14ADC
    1. 14.1 ADC Overview
    2. 14.2 ADC Operation
      1. 14.2.1  ADC Core
      2. 14.2.2  Voltage Reference Options
      3. 14.2.3  Generic Resolution Modes
      4. 14.2.4  Hardware Averaging
      5. 14.2.5  ADC Clocking
      6. 14.2.6  Common ADC Use Cases
      7. 14.2.7  Power Down Behavior
      8. 14.2.8  Sampling Trigger Sources and Sampling Modes
        1. 14.2.8.1 AUTO Sampling Mode
        2. 14.2.8.2 MANUAL Sampling Mode
      9. 14.2.9  Sampling Period
      10. 14.2.10 Conversion Modes
      11. 14.2.11 Data Format
      12. 14.2.12 Advanced Features
        1. 14.2.12.1 Window Comparator
        2. 14.2.12.2 DMA and FIFO Operation
        3. 14.2.12.3 Analog Peripheral Interconnection
      13. 14.2.13 Status Register
      14. 14.2.14 ADC Events
        1. 14.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 14.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 ADC12 Registers
  17. 15COMP
    1. 15.1 Comparator Overview
    2. 15.2 Comparator Operation
      1. 15.2.1  Comparator Configuration
      2. 15.2.2  Comparator Channels Selection
      3. 15.2.3  Comparator Output
      4. 15.2.4  Output Filter
      5. 15.2.5  Sampled Output Mode
      6. 15.2.6  Blanking Mode
      7. 15.2.7  Reference Voltage Generator
      8. 15.2.8  Comparator Hysteresis
      9. 15.2.9  Input SHORT Switch
      10. 15.2.10 Interrupt and Events Support
        1. 15.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.10.3 Generic Event Subscribers
    3. 15.3 COMP Registers
  18. 16OPA
    1. 16.1 OPA Overview
    2. 16.2 OPA Operation
      1. 16.2.1 Analog Core
      2. 16.2.2 Power Up Behavior
      3. 16.2.3 Inputs
      4. 16.2.4 Output
      5. 16.2.5 Clock Requirements
      6. 16.2.6 Chopping
      7. 16.2.7 OPA Amplifier Modes
        1. 16.2.7.1 General-Purpose Mode
        2. 16.2.7.2 Buffer Mode
        3. 16.2.7.3 OPA PGA Mode
          1. 16.2.7.3.1 Inverting PGA Mode
          2. 16.2.7.3.2 Non-inverting PGA Mode
        4. 16.2.7.4 Difference Amplifier Mode
        5. 16.2.7.5 Cascade Amplifier Mode
      8. 16.2.8 OPA Configuration Selection
      9. 16.2.9 Burnout Current Source
    3. 16.3 OA Registers
  19. 17GPAMP
    1. 17.1 GPAMP Overview
    2. 17.2 GPAMP Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 GPAMP Amplifier Modes
        1. 17.2.5.1 General-Purpose Mode
        2. 17.2.5.2 ADC Buffer Mode
        3. 17.2.5.3 Unity Gain Mode
      6. 17.2.6 Chopping
    3. 17.3 GPAMP Registers
  20. 18VREF
    1. 18.1 VREF Overview
    2. 18.2 VREF Operation
      1. 18.2.1 Internal Reference Generation
      2. 18.2.2 External Reference Input
      3. 18.2.3 Analog Peripheral Interface
    3. 18.3 VREF Registers
  21. 19UART
    1. 19.1 UART Overview
      1. 19.1.1 Purpose of the Peripheral
      2. 19.1.2 Features
      3. 19.1.3 Functional Block Diagram
    2. 19.2 UART Operation
      1. 19.2.1 Clock Control
      2. 19.2.2 Signal Descriptions
      3. 19.2.3 General Architecture and Protocol
        1. 19.2.3.1  Transmit Receive Logic
        2. 19.2.3.2  Bit Sampling
        3. 19.2.3.3  Majority Voting Feature
        4. 19.2.3.4  Baud Rate Generation
        5. 19.2.3.5  Data Transmission
        6. 19.2.3.6  Error and Status
        7. 19.2.3.7  Local Interconnect Network (LIN) Support
          1. 19.2.3.7.1 LIN Responder Transmission Delay
        8. 19.2.3.8  Flow Control
        9. 19.2.3.9  Idle-Line Multiprocessor
        10. 19.2.3.10 9-Bit UART Mode
        11. 19.2.3.11 RS485 Support
        12. 19.2.3.12 DALI Protocol
        13. 19.2.3.13 Manchester Encoding and Decoding
        14. 19.2.3.14 IrDA Encoding and Decoding
        15. 19.2.3.15 ISO7816 Smart Card Support
        16. 19.2.3.16 Address Detection
        17. 19.2.3.17 FIFO Operation
        18. 19.2.3.18 Loopback Operation
        19. 19.2.3.19 Glitch Suppression
      4. 19.2.4 Low Power Operation
      5. 19.2.5 Reset Considerations
      6. 19.2.6 Initialization
      7. 19.2.7 Interrupt and Events Support
        1. 19.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 19.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 19.2.8 Emulation Modes
    3. 19.3 UART Registers
  22. 20SPI
    1. 20.1 SPI Overview
      1. 20.1.1 Purpose of the Peripheral
      2. 20.1.2 Features
      3. 20.1.3 Functional Block Diagram
      4. 20.1.4 External Connections and Signal Descriptions
    2. 20.2 SPI Operation
      1. 20.2.1 Clock Control
      2. 20.2.2 General Architecture
        1. 20.2.2.1 Chip Select and Command Handling
          1. 20.2.2.1.1 Chip Select Control
          2. 20.2.2.1.2 Command Data Control
        2. 20.2.2.2 Data Format
        3. 20.2.2.3 Delayed data sampling
        4. 20.2.2.4 Clock Generation
        5. 20.2.2.5 FIFO Operation
        6. 20.2.2.6 Loopback mode
        7. 20.2.2.7 DMA Operation
        8. 20.2.2.8 Repeat Transfer mode
        9. 20.2.2.9 Low Power Mode
      3. 20.2.3 Protocol Descriptions
        1. 20.2.3.1 Motorola SPI Frame Format
        2. 20.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 20.2.4 Reset Considerations
      5. 20.2.5 Initialization
      6. 20.2.6 Interrupt and Events Support
        1. 20.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 20.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 20.2.7 Emulation Modes
    3. 20.3 SPI Registers
  23. 21I2C
    1. 21.1 I2C Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
      4. 21.1.4 Environment and External Connections
    2. 21.2 I2C Operation
      1. 21.2.1 Clock Control
        1. 21.2.1.1 Clock Select and I2C Speed
        2. 21.2.1.2 Clock Startup
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture
        1. 21.2.3.1  I2C Bus Functional Overview
        2. 21.2.3.2  START and STOP Conditions
        3. 21.2.3.3  Data Format with 7-Bit Address
        4. 21.2.3.4  Acknowledge
        5. 21.2.3.5  Repeated Start
        6. 21.2.3.6  SCL Clock Low Timeout
        7. 21.2.3.7  Clock Stretching
        8. 21.2.3.8  Dual Address
        9. 21.2.3.9  Arbitration
        10. 21.2.3.10 Multiple Controller Mode
        11. 21.2.3.11 Glitch Suppression
        12. 21.2.3.12 FIFO operation
          1. 21.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 21.2.3.13 Loopback mode
        14. 21.2.3.14 Burst Mode
        15. 21.2.3.15 DMA Operation
        16. 21.2.3.16 Low-Power Operation
      4. 21.2.4 Protocol Descriptions
        1. 21.2.4.1 I2C Controller Mode
          1. 21.2.4.1.1 Controller Configuration
          2. 21.2.4.1.2 Controller Mode Operation
          3. 21.2.4.1.3 Read On TX Empty
        2. 21.2.4.2 I2C Target Mode
          1. 21.2.4.2.1 Target Mode Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 21.2.8 Emulation Modes
    3. 21.3 I2C Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23Timers (TIMx)
    1. 23.1 TIMx Overview
      1. 23.1.1 TIMG Overview
        1. 23.1.1.1 TIMG Features
        2. 23.1.1.2 Functional Block Diagram
      2. 23.1.2 TIMA Overview
        1. 23.1.2.1 TIMA Features
        2. 23.1.2.2 Functional Block Diagram
      3. 23.1.3 TIMx Instance Configuration
    2. 23.2 TIMx Operation
      1. 23.2.1  Timer Counter
        1. 23.2.1.1 Clock Source Select and Prescaler
          1. 23.2.1.1.1 Internal Clock and Prescaler
          2. 23.2.1.1.2 External Signal Trigger
        2. 23.2.1.2 Repeat Counter (TIMA only)
      2. 23.2.2  Counting Mode Control
        1. 23.2.2.1 One-shot and Periodic Modes
        2. 23.2.2.2 Down Counting Mode
        3. 23.2.2.3 Up/Down Counting Mode
        4. 23.2.2.4 Up Counting Mode
        5. 23.2.2.5 Phase Load (TIMA only)
      3. 23.2.3  Capture/Compare Module
        1. 23.2.3.1 Capture Mode
          1. 23.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 23.2.3.1.1.1 CCP Input Edge Synchronization
            2. 23.2.3.1.1.2 CCP Input Pulse Conditions
            3. 23.2.3.1.1.3 Counter Control Operation
            4. 23.2.3.1.1.4 CCP Input Filtering
            5. 23.2.3.1.1.5 Input Selection
          2. 23.2.3.1.2 Use Cases
            1. 23.2.3.1.2.1 Edge Time Capture
            2. 23.2.3.1.2.2 Period Capture
            3. 23.2.3.1.2.3 Pulse Width Capture
            4. 23.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 23.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 23.2.3.1.3.1 QEI With 2-Signal
            2. 23.2.3.1.3.2 QEI With Index Input
            3. 23.2.3.1.3.3 QEI Error Detection
          4. 23.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 23.2.3.2 Compare Mode
          1. 23.2.3.2.1 Edge Count
      4. 23.2.4  Shadow Load and Shadow Compare
        1. 23.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 23.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 23.2.5  Output Generator
        1. 23.2.5.1 Configuration
        2. 23.2.5.2 Use Cases
          1. 23.2.5.2.1 Edge-Aligned PWM
          2. 23.2.5.2.2 Center-Aligned PWM
          3. 23.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 23.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 23.2.5.3 Forced Output
      6. 23.2.6  Fault Handler (TIMA only)
        1. 23.2.6.1 Fault Input Conditioning
        2. 23.2.6.2 Fault Input Sources
        3. 23.2.6.3 Counter Behavior With Fault Conditions
        4. 23.2.6.4 Output Behavior With Fault Conditions
      7. 23.2.7  Synchronization With Cross Trigger
        1. 23.2.7.1 Main Timer Cross Trigger Configuration
        2. 23.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 23.2.8  Low Power Operation
      9. 23.2.9  Interrupt and Event Support
        1. 23.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 23.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 23.2.10 Debug Handler (TIMA Only)
    3. 23.3 TIMx Registers
  26. 24LCD
    1. 24.1 LCD Introduction
      1. 24.1.1 LCD Operating Principle
      2. 24.1.2 LCD Mux Modes
      3. 24.1.3 Introduction
      4. 24.1.4 LCD Waveforms
    2. 24.2 LCD Clocking
    3. 24.3 Voltage Generation
      1. 24.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 24.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 24.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 24.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 24.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 24.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 24.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 24.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 24.3.9  Charge pump
      10. 24.3.10 Internal Reference Generation
    4. 24.4 Analog Mux
      1. 24.4.1 Static Mode
      2. 24.4.2 Non-Static 1/3 bias mode
      3. 24.4.3 Non-Static 1/4 bias mode
      4. 24.4.4 Low power mode switch controls
    5. 24.5 LCD Memory and output drive
      1. 24.5.1 LCD Memory organization
        1. 24.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 24.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 24.5.1.3 Configuring memory
        4. 24.5.1.4 Accessing memory and output drive
        5. 24.5.1.5 Blinking Override
    6. 24.6 IO Muxing
    7. 24.7 Interrupt Generation
    8. 24.8 Power Domains and Power Modes
    9. 24.9 LCD Registers
  27. 25RTC
    1. 25.1 Overview
      1. 25.1.1 RTC Instances
    2. 25.2 Basic Operation
    3. 25.3 Configuration
      1. 25.3.1  Clocking
      2. 25.3.2  Reading and Writing to RTC Peripheral Registers
      3. 25.3.3  Binary vs. BCD
      4. 25.3.4  Leap Year Handling
      5. 25.3.5  Calendar Alarm Configuration
      6. 25.3.6  Interval Alarm Configuration
      7. 25.3.7  Periodic Alarm Configuration
      8. 25.3.8  Calibration
        1. 25.3.8.1 Crystal Offset Error
          1. 25.3.8.1.1 Offset Error Correction Mechanism
        2. 25.3.8.2 Crystal Temperature Error
          1. 25.3.8.2.1 Temperature Drift Correction Mechanism
      9. 25.3.9  RTC Prescaler Extension
      10. 25.3.10 RTC Timestamp Capture
      11. 25.3.11 RTC Events
        1. 25.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 25.4 RTC Registers
  28. 26IWDT
    1. 26.1 IWDT Initialization after LFSS Reset
    2. 26.2 IWDT Clock Configuration
    3. 26.3 IWDT Period Selection
    4. 26.4 Debug Behavior of the IWDT
    5. 26.5 IWDT Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

2.6 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers

Table 2-16 lists the memory-mapped registers for the SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 registers. All register offset addresses not listed in Table 2-16 should be considered as reserved locations and the register contents should not be modified.

Table 2-16 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Registers
OffsetAcronymRegister NameSection
1020hIIDXSYSCTL interrupt indexSection 2.6.1
1028hIMASKSYSCTL interrupt maskSection 2.6.2
1030hRISSYSCTL raw interrupt statusSection 2.6.3
1038hMISSYSCTL masked interrupt statusSection 2.6.4
1040hISETSYSCTL interrupt setSection 2.6.5
1048hICLRSYSCTL interrupt clearSection 2.6.6
1050hNMIIIDXNMI interrupt indexSection 2.6.7
1060hNMIRISNMI raw interrupt statusSection 2.6.8
1070hNMIISETNMI interrupt setSection 2.6.9
1078hNMIICLRNMI interrupt clearSection 2.6.10
1100hSYSOSCCFGSYSOSC configurationSection 2.6.11
1104hMCLKCFGMain clock (MCLK) configurationSection 2.6.12
1138hGENCLKCFGGeneral clock configurationSection 2.6.13
113ChGENCLKENGeneral clock enable controlSection 2.6.14
1140hPMODECFGPower mode configurationSection 2.6.15
1150hFCCFrequency clock counter (FCC) countSection 2.6.16
1168hFLBANKSWAPFlash MAIN bank address swapSection 2.6.17
1170hSYSOSCTRIMUSERSYSOSC user-specified trimSection 2.6.18
1178hSYSMEMWEPROTSRAM write protection configurationSection 2.6.19
1200hWRITELOCKSYSCTL register write lockoutSection 2.6.20
1204hCLKSTATUSClock module (CKM) statusSection 2.6.21
1208hSYSSTATUSSystem status informationSection 2.6.22
1220hRSTCAUSEReset causeSection 2.6.23
1300hRESETLEVELReset level for application-triggered reset commandSection 2.6.24
1304hRESETCMDExecute an application-triggered reset commandSection 2.6.25
1308hBORTHRESHOLDBOR threshold selectionSection 2.6.26
130ChBORCLRCMDSet the BOR thresholdSection 2.6.27
1310hSYSOSCFCLCTLSYSOSC frequency correction loop (FCL) ROSC enableSection 2.6.28
131ChSHDNIORELSHUTDOWN IO release controlSection 2.6.29
1320hEXRSTPINDisable the reset function of the NRST pinSection 2.6.30
1324hSYSSTATUSCLRClear sticky bits of SYSSTATUSSection 2.6.31
1328hSWDCFGDisable the SWD function on the SWD pinsSection 2.6.32
132ChFCCCMDFrequency clock counter start captureSection 2.6.33
1380hPMUOPAMPGPAMP controlSection 2.6.34
1400hSHUTDNSTORE0Shutdown storage memory (byte 0)Section 2.6.35
1404hSHUTDNSTORE1Shutdown storage memory (byte 1)Section 2.6.36
1408hSHUTDNSTORE2Shutdown storage memory (byte 2)Section 2.6.37
140ChSHUTDNSTORE3Shutdown storage memory (byte 3)Section 2.6.38

Complex bit access types are encoded to fit into small table cells. Table 2-17 shows the codes that are used for access types in this section.

Table 2-17 SYSCTL_L1105_L1106_L1303_L1304_L1305_L1306_L1343_L1344_L1345_L1346 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

2.6.1 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Table 2-18.

Return to the Summary Table.

SYSCTL interrupt index

Table 2-18 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0STATR0hThe SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0h = No interrupt pending
1h = LFOSCGOOD interrupt pending
2h = BORLVL interrupt pending
3h = ANACLKERR interrupt pending

2.6.2 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Table 2-19.

Return to the Summary Table.

SYSCTL interrupt mask

Table 2-19 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ANACLKERRR/W0hEnable or disable the analog clocking consistency error interrupt.
0h = Interrupt disabled
1h = Interrupt enabled
1BORLVLR/W0hEnable or disable the BORLVL interrupt. BORLVL indicates that a BORLVL violation has occurred.
0h = Interrupt disabled
1h = Interrupt enabled
0LFOSCGOODR/W0hEnable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
0h = Interrupt disabled
1h = Interrupt enabled

2.6.3 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Table 2-20.

Return to the Summary Table.

SYSCTL raw interrupt status

Table 2-20 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ANACLKERRR0hRaw status of the analog clocking consistency error interrupt.
0h = No interrupt pending
1h = Interrupt pending
1BORLVLR0hRaw status of the BORLVL interrupt.
0h = No interrupt pending
1h = Interrupt pending
0LFOSCGOODR0hRaw status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

2.6.4 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Table 2-21.

Return to the Summary Table.

SYSCTL masked interrupt status

Table 2-21 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ANACLKERRR0hMasked status of the analog clocking consistency error interrupt.
0h = No interrupt pending
1h = Interrupt pending
1BORLVLR0hMasked status of the BORLVL interrupt.
0h = No interrupt pending
1h = Interrupt pending
0LFOSCGOODR0hMasked status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

2.6.5 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Table 2-22.

Return to the Summary Table.

SYSCTL interrupt set

Table 2-22 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ANACLKERRW1S0hSet the analog clocking consistency error interrupt.
0h = Writing 0h has no effect
1h = Set interrupt
1BORLVLW1S0hSet the BORLVL interrupt.
0h = Writing 0h has no effect
1h = Set interrupt
0LFOSCGOODW1S0hSet the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Set interrupt

2.6.6 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Table 2-23.

Return to the Summary Table.

SYSCTL interrupt clear

Table 2-23 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ANACLKERRW1C0hClear the analog clocking consistency error interrupt.
0h = Writing 0h has no effect
1h = Clear interrupt
1RESERVEDR0h
0LFOSCGOODW1C0hClear the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Clear interrupt

2.6.7 NMIIIDX Register (Offset = 1050h) [Reset = 00000000h]

NMIIIDX is shown in Table 2-24.

Return to the Summary Table.

NMI interrupt index

Table 2-24 NMIIIDX Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0STATR0hThe NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
0h = No NMI pending
1h = BOR Threshold NMI pending
2h = 2

2.6.8 NMIRIS Register (Offset = 1060h) [Reset = 00000000h]

NMIRIS is shown in Table 2-25.

Return to the Summary Table.

NMI raw interrupt status

Table 2-25 NMIRIS Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1WWDT0R0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLR0hRaw status of the BORLVL NMI
0h = No interrupt pending
1h = Interrupt pending

2.6.9 NMIISET Register (Offset = 1070h) [Reset = 00000000h]

NMIISET is shown in Table 2-26.

Return to the Summary Table.

NMI interrupt set

Table 2-26 NMIISET Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1WWDT0W1S0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLW1S0hSet the BORLVL NMI
0h = Writing 0h has no effect
1h = Set interrupt

2.6.10 NMIICLR Register (Offset = 1078h) [Reset = 00000000h]

NMIICLR is shown in Table 2-27.

Return to the Summary Table.

NMI interrupt clear

Table 2-27 NMIICLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1WWDT0W1C0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLW1C0hClear the BORLVL NMI
0h = Writing 0h has no effect
1h = Clear interrupt

2.6.11 SYSOSCCFG Register (Offset = 1100h) [Reset = 0002XXXXh]

SYSOSCCFG is shown in Table 2-28.

Return to the Summary Table.

SYSOSC configuration

Table 2-28 SYSOSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17FASTCPUEVENTR/W1hFASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.
0h = An interrupt to the CPU will not assert a fast clock request
1h = An interrupt to the CPU will assert a fast clock request
16BLOCKASYNCALLR/W0hBLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
0h = Asynchronous fast clock requests are controlled by the requesting peripheral
1h = All asynchronous fast clock requests are blocked
15-11RESERVEDR0h
10DISABLER/W0hDISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.
0h = Do not disable SYSOSC
1h = Disable SYSOSC immediately and source MCLK and ULPCLK from LFCLK
9DISABLESTOPR/W0hDISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.
0h = Do not disable SYSOSC in STOP mode
1h = Disable SYSOSC in STOP mode and source ULPCLK from LFCLK
8USE4MHZSTOPR/W0hUSE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.
0h = Do not gear shift the SYSOSC to 4MHz in STOP mode
1h = Gear shift SYSOSC to 4MHz in STOP mode
7-2RESERVEDR0h
1-0FREQR/W0hTarget operating frequency for the system oscillator (SYSOSC)
0h = Base frequency (32MHz)
1h = Low frequency (4MHz)
2h = User-trimmed frequency (16 or 24 MHz)
3h = Reserved

2.6.12 MCLKCFG Register (Offset = 1104h) [Reset = 000XX2X0h]

MCLKCFG is shown in Table 2-29.

Return to the Summary Table.

Main clock (MCLK) configuration

Table 2-29 MCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22MCLKDEADCHKR/W0hMCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled.
0h = The MCLK dead check monitor is disabled
1h = The MCLK dead check monitor is enabled
21STOPCLKSTBYR/W0hSTOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request.
0h = ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode
1h = ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1
20USELFCLKR/W0hUSELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source. Note that setting USELFCLK does not disable SYSOSC, and SYSOSC remains available for direct use by analog modules.
0h = MCLK will not use the low frequency clock (LFCLK)
1h = MCLK will use the low frequency clock (LFCLK)
19-13RESERVEDR0h
12USEMFTICKR/W0hUSEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1).
0h = The 4MHz rate MFCLK to peripherals is disabled
1h = The 4MHz rate MFCLK to peripherals is enabled.
11-8FLASHWAITR/W2hFLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK.
0h = No flash wait states are applied
1h = One flash wait state is applied
2h = 2 flash wait states are applied
7-4RESERVEDR0h
3-0MDIVR/W0hMDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC. MDIV=0h corresponds to /1 (no divider). MDIV=1h corresponds to /2 (divide-by-2). MDIV=Fh corresponds to /16 (divide-by-16). MDIV may be set between /1 and /16 on an integer basis.

2.6.13 GENCLKCFG Register (Offset = 1138h) [Reset = 0000XX0Xh]

GENCLKCFG is shown in Table 2-30.

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General clock configuration

Table 2-30 GENCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-24FCCTRIGCNTR/W0hFCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified.
23-22ANACPUMPCFGR/W0hANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method.
0h = VBOOST is enabled on request from a COMP, GPAMP, or OPA
1h = VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled
2h = VBOOST is always enabled
21FCCLVLTRIGR/W0hFCCLVLTRIG selects the frequency clock counter (FCC) trigger mode.
0h = Rising edge to rising edge triggered
1h = Level triggered
20FCCTRIGSRCR/W0hFCCTRIGSRC selects the frequency clock counter (FCC) trigger source.
0h = FCC trigger is the external pin
1h = FCC trigger is the LFXT/LFCLK_IN mux output
19-16FCCSELCLKR/W0hFCCSELCLK selects the frequency clock counter (FCC) clock source.
0h = FCC clock is MCLK
1h = FCC clock is SYSOSC
3h = FCC clock is the CLK_OUT selection
7h = FCC clock is the FCCIN external input
15-8RESERVEDR0h
7EXCLKDIVENR/W0hEXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block.
0h = Clock divider is disabled (passthrough, EXCLKDIVVAL is not applied)
1h = Clock divider is enabled (EXCLKDIVVAL is applied)
6-4EXCLKDIVVALR/W0hEXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block.
0h = CLK_OUT source is divided by 2
1h = CLK_OUT source is divided by 4
2h = CLK_OUT source is divided by 6
3h = CLK_OUT source is divided by 8
4h = CLK_OUT source is divided by 10
5h = CLK_OUT source is divided by 12
6h = CLK_OUT source is divided by 14
7h = CLK_OUT source is divided by 16
3RESERVEDR0h
2-0EXCLKSRCR/W0hEXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled
0h = CLK_OUT is SYSOSC
1h = CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled)
2h = CLK_OUT is LFCLK
3h = CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled)

2.6.14 GENCLKEN Register (Offset = 113Ch) [Reset = 0000000Xh]

GENCLKEN is shown in Table 2-31.

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General clock enable control

Table 2-31 GENCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4MFPCLKENR/W0hMFPCLKEN enables the middle frequency precision clock (MFPCLK).
0h = MFPCLK is disabled
1h = MFPCLK is enabled
3-1RESERVEDR0h
0EXCLKENR/W0hEXCLKEN enables the CLK_OUT external clock output block.
0h = CLK_OUT block is disabled
1h = CLK_OUT block is enabled

2.6.15 PMODECFG Register (Offset = 1140h) [Reset = 000000XXh]

PMODECFG is shown in Table 2-32.

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Power mode configuration

Table 2-32 PMODECFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5SYSSRAMONSTOPR/W0hSYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode.
0h = SRAM controller is disabled in STOP mode (lower power consumption)
1h = SRAM controller is left enabled in STOP mode (faster wake-up)
4-2RESERVEDR0h
1-0DSLEEPR/W0hDSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
0h = STOP mode is entered
1h = STANDBY mode is entered
2h = SHUTDOWN mode is entered
3h = Reserved

2.6.16 FCC Register (Offset = 1150h) [Reset = 00000000h]

FCC is shown in Table 2-33.

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Frequency clock counter (FCC) count

Table 2-33 FCC Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-0DATAR0hFrequency clock counter (FCC) count value.

2.6.17 FLBANKSWAP Register (Offset = 1168h) [Reset = 00XXXXXXh]

FLBANKSWAP is shown in Table 2-34.

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Flash MAIN bank address swap

Table 2-34 FLBANKSWAP Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYR/W0hThe key value of 58h (88) must be written with USEUPPER to change the bank swap configuration.
58h = Issue write
23-1RESERVEDR0h
0USEUPPERR0hUSEUPPER selects the flash MAIN region bank swap configuration. To swap MAIN banks, set USEUPPER while writing the KEY value to the KEY field.
0h = Normal (default) memory map addressing scheme
1h = Flash upper region address space swapped with lower region

2.6.18 SYSOSCTRIMUSER Register (Offset = 1170h) [Reset = 0000X0XXh]

SYSOSCTRIMUSER is shown in Table 2-35.

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SYSOSC user-specified trim

Table 2-35 SYSOSCTRIMUSER Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-20RDIVR/W0hRDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency.
19-16RESFINER/W0hRESFINE specifies the resister fine trim. This value changes with the target frequency.
15-14RESERVEDR0h
13-8RESCOARSER/W0hRESCOARSE specifies the resister coarse trim. This value changes with the target frequency.
7RESERVEDR0h
6-4CAPR/W0hCAP specifies the SYSOSC capacitor trim. This value changes with the target frequency.
3-2RESERVEDR0h
1-0FREQR/W0hFREQ specifies the target user-trimmed frequency for SYSOSC.
1h = 16MHz user frequency
2h = 24MHz user frequency
3h = Reserved

2.6.19 SYSMEMWEPROT Register (Offset = 1178h) [Reset = 00000000h]

SYSMEMWEPROT is shown in Table 2-36.

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SRAM write protection configuration

Table 2-36 SYSMEMWEPROT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0PROTR/W0hPROT is a bitwise field which specifies the SRAM write protection scheme. The SRAM write protection is enabled on a 1kB boundary basis, with each bit in PORT corresponding to a 1kB region of SRAM. The LSB of PORT corresponding to the lowest 1kB of SRAM, with each subsequent bit corresponding to the next 1kB of SRAM up to a maximum of 32 1kB regions (if present on a device). To protect a 1kB region, set the bit in PROT which corresponds to the region.

2.6.20 WRITELOCK Register (Offset = 1200h) [Reset = 00000000h]

WRITELOCK is shown in Table 2-37.

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SYSCTL register write lockout

Table 2-37 WRITELOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0ACTIVER/W0hACTIVE controls whether critical SYSCTL registers are write protected or not.
0h = Allow writes to lockable registers
1h = Disallow writes to lockable registers

2.6.21 CLKSTATUS Register (Offset = 1204h) [Reset = XXXXXXXXh]

CLKSTATUS is shown in Table 2-38.

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Clock module (CKM) status

Table 2-38 CLKSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31ANACLKERRR0hANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected.
0h = No analog clock errors detected
1h = Analog clock error detected
30OPAMPCLKERRR0hOPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected.
0h = No OPA clock generation errors detected
1h = OPA clock generation error detected
29-26RESERVEDR0h
25FCCDONER0hFCCDONE indicates when a frequency clock counter capture is complete.
0h = FCC capture is not done
1h = FCC capture is done
24FCLMODER0hFCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled.
0h = SYSOSC FCL is disabled
1h = SYSOSC FCL is enabled
23-18RESERVEDR0h
17CURMCLKSELR0hCURMCLKSEL indicates if MCLK is currently sourced from LFCLK.
0h = MCLK is not sourced from LFCLK
1h = MCLK is sourced from LFCLK
16-12RESERVEDR0h
11LFOSCGOODR0hLFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use.
0h = LFOSC is not ready
1h = LFOSC is ready
10-8RESERVEDR0h
7-6LFCLKMUXR0hLFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input.
0h = LFCLK is sourced from the internal LFOSC
1h = LFCLK is sourced from the LFXT (crystal)
2h = LFCLK is sourced from LFCLK_IN (external digital clock input)
5-2RESERVEDR0h
1-0SYSOSCFREQR0hSYSOSCFREQ indicates the current SYSOSC operating frequency.
0h = SYSOSC is at base frequency (32MHz)
1h = SYSOSC is at low frequency (4MHz)
2h = SYSOSC is at the user-trimmed frequency (16 or 24MHz)
3h = Reserved

2.6.22 SYSSTATUS Register (Offset = 1208h) [Reset = XXXXXXX0h]

SYSSTATUS is shown in Table 2-39.

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System status information

Table 2-39 SYSSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30REBOOTATTEMPTSR0hREBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts.
29-15RESERVEDR0h
14SHDNIOLOCKR0hSHDNIOLOCK indicates when IO is locked due to SHUTDOWN
0h = IO IS NOT Locked due to SHUTDOWN
1h = IO IS Locked due to SHUTDOWN
13SWDCFGDISR0hSWDCFGDIS indicates when user has disabled the use of SWD Port
0h = SWD Port Enabled
1h = SWD Port Disabled
12EXTRSTPINDISR0hEXTRSTPINDIS indicates when user has disabled the use of external reset pin
0h = External Reset Pin Enabled
1h = External Reset Pin Disabled
11-7RESERVEDR0h
6PMUIREFGOODR0hPMUIREFGOOD is set by hardware when the PMU current reference is ready.
0h = IREF is not ready
1h = IREF is ready
5ANACPUMPGOODR0hANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready.
0h = VBOOST is not ready
1h = VBOOST is ready
4BORLVLR0hBORLVL indicates if a BOR event occurred and the BOR threshold was switched to BOR0 by hardware.
0h = No BOR violation occurred
1h = A BOR violation occurred and the BOR threshold was switched to BOR0
3-2BORCURTHRESHOLDR0hBORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration.
0h = Default minimum threshold; a BOR0- violation triggers a BOR
1h = A BOR1- violation generates a BORLVL interrupt
2h = A BOR2- violation generates a BORLVL interrupt
3h = A BOR3- violation generates a BORLVL interrupt
1FLASHSECR0hFLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC).
0h = No flash ECC single bit error detected
1h = Flash ECC single bit error was detected and corrected
0FLASHDEDR0hFLASHDED indicates if a flash ECC double bit error was detected (DED).
0h = No flash ECC double bit error detected
1h = Flash ECC double bit error detected

2.6.23 RSTCAUSE Register (Offset = 1220h) [Reset = 00000000h]

RSTCAUSE is shown in Table 2-40.

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Reset cause

Table 2-40 RSTCAUSE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
0h = No reset since last read
1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
2h = NRST triggered POR (greater than 1s hold)
3h = Software triggered POR
4h = BOR0- violation
5h = SHUTDOWN mode exit
8h = Non-PMU trim parity fault
9h = Fatal clock failure
Ch = NRST triggered BOOTRST (less than 1s hold)
Dh = Software triggered BOOTRST
Eh = WWDT0 violation
10h = BSL exit
11h = BSL entry
13h = WWDT1 violation
14h = Flash uncorrectable ECC error
15h = CPULOCK violation
1Ah = Debug triggered SYSRST
1Bh = Software triggered SYSRST
1Ch = Debug triggered CPURST
1Dh = Software triggered CPURST

2.6.24 RESETLEVEL Register (Offset = 1300h) [Reset = 00000000h]

RESETLEVEL is shown in Table 2-41.

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Reset level for application-triggered reset command

Table 2-41 RESETLEVEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0LEVELR/W0hLEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
0h = Issue a SYSRST (CPU plus peripherals only)
1h = Issue a BOOTRST (CPU, peripherals, and boot configuration routine)
2h = Issue a SYSRST and enter the boot strap loader (BSL)
3h = Issue a power-on reset (POR)
4h = Issue a SYSRST and exit the boot strap loader (BSL)

2.6.25 RESETCMD Register (Offset = 1304h) [Reset = 00XXXXXXh]

RESETCMD is shown in Table 2-42.

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Execute an application-triggered reset command

Table 2-42 RESETCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of E4h (228) must be written to KEY together with GO to trigger the reset.
E4h = Issue reset
23-1RESERVEDR0h
0GOW0hExecute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
1h = Issue reset

2.6.26 BORTHRESHOLD Register (Offset = 1308h) [Reset = 00000000h]

BORTHRESHOLD is shown in Table 2-43.

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BOR threshold selection

Table 2-43 BORTHRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1-0LEVELR/W0hLEVEL specifies the desired BOR threshold and BOR mode.
0h = Default minimum threshold; a BOR0- violation triggers a BOR
1h = A BOR1- violation generates a BORLVL interrupt
2h = A BOR2- violation generates a BORLVL interrupt
3h = A BOR3- violation generates a BORLVL interrupt

2.6.27 BORCLRCMD Register (Offset = 130Ch) [Reset = 00XXXXXXh]

BORCLRCMD is shown in Table 2-44.

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Set the BOR threshold

Table 2-44 BORCLRCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.
C7h = Issue clear
23-1RESERVEDR0h
0GOW0hGO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.
1h = Issue clear

2.6.28 SYSOSCFCLCTL Register (Offset = 1310h) [Reset = 00XXXXXXh]

SYSOSCFCLCTL is shown in Table 2-45.

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SYSOSC frequency correction loop (FCL) ROSC enable

Table 2-45 SYSOSCFCLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
2Ah = Issue Command
23-1RESERVEDR0h
0SETUSEFCLW0hSet SETUSEFCL to enable the frequency correction loop in SYSOSC. An appropriate resistor must be populated on the ROSC pin. Once enabled, this state is locked until the next BOOTRST.
1h = Enable the SYSOSC FCL

2.6.29 SHDNIOREL Register (Offset = 131Ch) [Reset = 00XXXXXXh]

SHDNIOREL is shown in Table 2-46.

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SHUTDOWN IO release control

Table 2-46 SHDNIOREL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 91h must be written to KEY together with RELEASE to set RELEASE.
91h = Issue command
23-1RESERVEDR0h
0RELEASEW0hSet RELEASE to release the IO after a SHUTDOWN mode exit.
1h = Release IO

2.6.30 EXRSTPIN Register (Offset = 1320h) [Reset = 00XXXXXXh]

EXRSTPIN is shown in Table 2-47.

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Disable the reset function of the NRST pin

Table 2-47 EXRSTPIN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 1Eh must be written together with DISABLE to disable the reset function.
1Eh = Issue command
23-1RESERVEDR0h
0DISABLEW0hSet DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
0h = Reset function of NRST pin is enabled
1h = Reset function of NRST pin is disabled

2.6.31 SYSSTATUSCLR Register (Offset = 1324h) [Reset = 00XXXXXXh]

SYSSTATUSCLR is shown in Table 2-48.

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Clear sticky bits of SYSSTATUS

Table 2-48 SYSSTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value CEh (206) must be written to KEY together with ALLECC to clear the ECC state.
CEh = Issue command
23-1RESERVEDR0h
0ALLECCW0hSet ALLECC to clear all ECC related SYSSTATUS indicators.
1h = Clear ECC error state

2.6.32 SWDCFG Register (Offset = 1328h) [Reset = 00XXXXXXh]

SWDCFG is shown in Table 2-49.

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Disable the SWD function on the SWD pins

Table 2-49 SWDCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.
62h = Issue command
23-1RESERVEDR0h
0DISABLEW0hSet DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.
1h = Disable SWD function on SWD pins

2.6.33 FCCCMD Register (Offset = 132Ch) [Reset = 00XXXXXXh]

FCCCMD is shown in Table 2-50.

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Frequency clock counter start capture

Table 2-50 FCCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 0Eh (14) must be written with GO to start a capture.
0Eh = Issue command
23-1RESERVEDR0h
0GOW0hSet GO to start a capture with the frequency clock counter (FCC).
1h = 1

2.6.34 PMUOPAMP Register (Offset = 1380h) [Reset = 000000X0h]

PMUOPAMP is shown in Table 2-51.

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GPAMP control

Table 2-51 PMUOPAMP Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h
10CHOPCLKMODER/W0hCHOPCLKMODE selects the GPAMP chopping mode.
0h = Chopping disabled
1h = Standard chopping
9-8CHOPCLKFREQR/W0hCHOPCLKFREQ selects the GPAMP chopping clock frequency
0h = 16kHz
1h = 8kHz
2h = 4kHz
3h = 2kHz
7RESERVEDR0h
6OUTENABLER/W0hSet OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin
0h = GPAMP_OUT signal is not connected to the GPAMP_OUT pin
1h = GPAMP_OUT signal is connected to the GPAMP_OUT pin
5-4RRIR/W0hRRI selects the rail-to-rail input mode.
0h = PMOS input pairs
1h = NMOS input pairs
2h = Rail-to-rail mode
3h = Sample channel 0
3-2NSELR/W0hNSEL selects the GPAMP negative channel input.
0h = GPAMP_OUT pin connected to negative channel
1h = GPAMP_IN- pin connected to negative channel
2h = GPAMP_OUT signal connected to negative channel
3h = No channel selected
1PCHENABLER/W0hSet PCHENABLE to enable the positive channel input.
0h = Positive channel disabled
1h = GPAMP_IN+ connected to positive channel
0ENABLER/W0hSet ENABLE to turn on the GPAMP.
0h = GPAMP is disabled
1h = GPAMP is enabled

2.6.35 SHUTDNSTORE0 Register (Offset = 1400h) [Reset = 00000000h]

SHUTDNSTORE0 is shown in Table 2-52.

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Shutdown storage memory (byte 0)

Table 2-52 SHUTDNSTORE0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9PARITYERRR0hParity error for SHUTDNSTORE0
8PARITYR/W0hParity for SHUTDNSTORE0
7-0DATAR/W0hShutdown storage byte 0

2.6.36 SHUTDNSTORE1 Register (Offset = 1404h) [Reset = 00000000h]

SHUTDNSTORE1 is shown in Table 2-53.

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Shutdown storage memory (byte 1)

Table 2-53 SHUTDNSTORE1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9PARITYERRR0hParity error for SHUTDNSTORE1
8PARITYR/W0hParity for SHUTDNSTORE1
7-0DATAR/W0hShutdown storage byte 1

2.6.37 SHUTDNSTORE2 Register (Offset = 1408h) [Reset = 00000000h]

SHUTDNSTORE2 is shown in Table 2-54.

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Shutdown storage memory (byte 2)

Table 2-54 SHUTDNSTORE2 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9PARITYERRR0hParity error for SHUTDNSTORE2
8PARITYR/W0hParity for SHUTDNSTORE2
7-0DATAR/W0hShutdown storage byte 2

2.6.38 SHUTDNSTORE3 Register (Offset = 140Ch) [Reset = 00000000h]

SHUTDNSTORE3 is shown in Table 2-55.

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Shutdown storage memory (byte 3)

Table 2-55 SHUTDNSTORE3 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9PARITYERRR0hParity error for SHUTDNSTORE3
8PARITYR/W0hParity for SHUTDNSTORE3
7-0DATAR/W0hShutdown storage byte 3