SLAU929 April 2024 MSPM0C1104 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1
MSPM0 GPIO functionality covers all of the features offered by the ATmega and ATtiny devices, with additional functionality. Microchip uses the term GPIO to refer to all the functionality responsible for managing the device pins. However, MSPM0 uses a slightly different nomenclature, namely:
Together MSPM0 GPIO and IOMUX cover the same functionality as Microchip's GPIO. MSPM0 devices also offer a number of additional functions that are unavailable for Microchip ATmega and ATtiny devices.
Feature | ATmega | ATtiny | MSPM0G, MSPM0L,MSPM0C |
---|---|---|---|
Output modes | Push-pull Open drain with pullup |
Push-pull Open drain with pullup |
Push-pull Open drain with pullup or pulldown |
GPIO speed selection | Data unavailable | 2.5ns rise time, 2.0ns fall time | ODIO pins: 120ns All others: 0.3*fmax = 3.75ns @ 80MHz |
High-drive GPIO | Data unavailable | 100mA combined per pin group | Equivalent, called High Drive IO (HDIO) |
Input modes | Floating Pull-up Analog |
Floating Pull-up Analog |
Equivalent |
Atomic bit set and reset | Yes | Yes | Equivalent |
Alternate functions | Configured with configuration register | Configured with configuration register | Equivalent MSPM0 uses IOMUX |
Wake-up | GPIO pin state change | GPIO pin state change | Equivalent |
GPIO controlled by DMA | No | No | Yes |
User controlled input filtering to reject glitches less than 1, 3, or 8 ULPCLK periods | No | No | Yes |
User controllable input hysteresis | No | No | Yes |
Information about GPIO code examples can be found in the MSPM0 SDK examples guide.