SLAU929 April 2024 MSPM0C1104 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1
MSPM0 and Microchip 8-bit MCUs both support serial peripheral interface (SPI). Overall, MSPM0 and ATtiny/ATmega SPI support is comparable with the difference listed in Table 4-3.
Feature | ATmega | ATtiny | MSPM0 |
---|---|---|---|
Controller or peripheral operation | Yes | Yes | Yes |
Data bit width (controller mode) | 8 bits | 8 bits | 4 to 16 bit |
Data bit width (peripheral mode) | 8 bits | 8 bits | 7 to 16 bit |
Maximum speed | 8MHz | 10MHz | MSPM0C: 12 MHz |
MSPM0L: 16MHz | |||
MSPM0G: 32MHz | |||
Full-duplex transfers | Yes | Yes | Yes |
Half-duplex transfer (bidirectional data line) | No | No | No |
Simplex transfers (unidirectional data line) | Yes | Yes | Yes |
Hardware chip select management | No | No | Yes |
Programmable clock polarity and phase | Yes | Yes | Yes |
Programmable data order with MSB-first or LSB-first shifting | Yes | Yes | Yes |
SPI format support | No | No | Motorola, TI, MICROWIRE |
Hardware CRC | No | No | No, MSPM0 offers SPI parity mode |
TX FIFO depth | 1 | 1 | 4 |
RX FIFO depth | 1 | 2 | 4 |