SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
Figure 7-66 shows the RESET register. Table 7-59 describes the RESET register. RESET command does not reset the PC bit in the STATUS3 register to the power-on default value.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||||
RESET[7:0] | |||||||||||||||
W-00000000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RESET | W | 00000000 | Write 0xC3 to the RESET register to reset all writable registers to their default values. If the logic is in stand-alone mode, writing 0xC3 returns the channel enable state machines to the LOAD state. Watchdog timer is disabled. |
Write 0xD4 to the RESET register to reset all writable registers to their default values. If the logic is in stand-alone mode, reading the STATUS3 register to clear the CMWTO bits and then writing 0xD4 to the RESET register returns the channel enable state machines to the DETECT state. Watchdog timer is enabled. | ||||
This register is write-only. Reads of this register return 0. |