SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The LHCFG2 register contains bits associated with enabling fault handling for both channels and configuring fault timer in limp-home mode. Figure 7-53 shows the LHCFG2 register. Table 7-42 describes the LHCFG2 register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LHIFT[1:0] | LH2TSFL | LH2HSILIMFL | LH2LSILIMFL | LH1TSFL | LH1HSILIMFL | LH1LSILIMFL | |
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | LHIFT | R/W | 00 | LHIFT sets the counter limit for the ILIM fault timer in limp-home mode. 00 = 3.6 ms fault timer 01 = 7.2 ms fault timer 10 = 14.4 ms fault timer 11 = 28.8 ms fault timer |
5 | LH2TSFL | R/W | 0 | Channel 2 thermal shutdown fault response in limp-home mode 0 = Channel 2 auto-restarts based on internal temperature hysteresis. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
4 | LH2HSILIMFL | R/W | 0 | Channel 2 high-side FET current limit fault response in limp-home mode 0 = Channel 2 auto-restarts after the ILIM fault timer has expired. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
3 | LH2LSILIMFL | R/W | 0 | Channel 2 low-side FET current limit fault response in limp-home mode 0 = Channel 2 auto-restarts after the ILIM fault timer has expired. 1 = Channel 2 is latched off; CH2EN bit is reset and channel 2 is disabled until the CH2EN bit is programmed high by SPI command. |
2 | LH1TSFL | R/W | 0 | Channel 1 thermal shutdown fault response in limp-home mode 0 = Channel 1 auto-restarts based on internal temperature hysteresis. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |
1 | LH1HSILIMFL | R/W | 0 | Channel 1 high-side FET current limit fault response in limp-home mode 0 = Channel 1 auto-restarts after the ILIM fault timer has expired. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |
0 | LH1LSILIMFL | R/W | 0 | Channel 1 low-side FET current limit fault response in limp-home mode 0 = Channel 1 auto-restarts after the ILIM fault timer has expired. 1 = Channel 1 is latched off; CH1EN bit is reset and channel 1 is disabled until the CH1EN bit is programmed high by SPI command. |