SLUSD66D September   2019  – February 2021 TPS92520-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Buck Converter Switching Operation
      2. 7.3.2  Switching Frequency and Adaptive On-Time Control
      3. 7.3.3  Minimum On-Time, Off-Time, and Inductor Ripple
      4. 7.3.4  LED Current Regulation and Error Amplifier
      5. 7.3.5  Start-up Sequence
      6. 7.3.6  Analog Dimming and Forced Continuous Conduction Mode
      7. 7.3.7  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      8. 7.3.8  Internal PWM Dimming
      9. 7.3.9  Shunt FET Dimming or Matrix Beam Application
      10. 7.3.10 Bias Supply
      11. 7.3.11 Bootstrap Supply
      12. 7.3.12 ADC
        1. 7.3.12.1 Input Voltage Measurement: VINx
        2. 7.3.12.2 LED Voltage Measurement: CSNx
        3. 7.3.12.3 Bias Supply Measurement: V5D
        4. 7.3.12.4 External Limp-Home Input Measurement: LHI
        5. 7.3.12.5 Junction Temperature Measurement: TEMP
      13. 7.3.13 Faults and Diagnostics
      14. 7.3.14 Output Short Circuit Fault
      15. 7.3.15 Output Open Circuit Fault
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power On Reset (POR)
      2. 7.4.2 Detect SPI Communication
      3. 7.4.3 Standalone Mode
      4. 7.4.4 Load Mode
      5. 7.4.5 Run Mode
      6. 7.4.6 Sleep Mode
      7. 7.4.7 Limp-Home Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Command Frame
      3. 7.5.3 Response Frame
        1. 7.5.3.1 Read Response Frame Format
        2. 7.5.3.2 Write Response Frame Format
        3. 7.5.3.3 Write Error/POR Frame Format
      4. 7.5.4 SPI Error
      5. 7.5.5 SPI for Multiple Slave Devices in Parallel Configuration
      6. 7.5.6 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
        1. 7.6.1.1 SYSCFG1 Register (address = 0x00) [reset = 0x10]
        2. 7.6.1.2 SYSCFG2 Register (address = 0x01) [reset = 0x00]
        3. 7.6.1.3 CMWTAP Register (address = 0x02) [reset = 0x08]
      2. 7.6.2 STATUS Registers
        1. 7.6.2.1 STATUS1 Register (address = 0x03)
        2. 7.6.2.2 STATUS2 Register (address = 0x04)
        3. 7.6.2.3 STATUS3 Register (address = 0x05)
      3. 7.6.3 Device Control Registers
        1. 7.6.3.1  Thermal Warning Limit (address = 0x06) [reset = 0x8A]
        2. 7.6.3.2  SLEEP Command (address = 0x07) [reset = 0x00]
        3. 7.6.3.3  CH1IADJL Control Register (address = 0x08) [reset = 0x00]
        4. 7.6.3.4  CH1IADJH Control Register (address = 0x09) [reset = 0x00]
        5. 7.6.3.5  CH2IADJL Control Register (address = 0x0A) [reset = 0x00]
        6. 7.6.3.6  CH2IADJH Control Register (address = 0x0B) [reset = 0x00]
        7. 7.6.3.7  PWMDIV Register (address = 0x0C) [reset = 0x04]
        8. 7.6.3.8  CH1PWML Register (address = 0x0D) [reset = 0x00]
        9. 7.6.3.9  CH1PWMH Register (address = 0x0E) [reset = 0x00]
        10. 7.6.3.10 CH2PWML Register (address = 0x0F) [reset = 0x00]
        11. 7.6.3.11 CH2PWMH Register (address = 0x10) [reset = 0x00]
        12. 7.6.3.12 CH1TON Register (address = 0x11) [reset = 0x07]
        13. 7.6.3.13 CH2TON Register (address = 0x12) [reset = 0x07]
      4. 7.6.4 ADC Measurements
        1. 7.6.4.1  CH1VIN Measurement (address = 0x13)
        2. 7.6.4.2  CH1VLED Measurement (address = 0x14)
        3. 7.6.4.3  CH1VLEDON Measurement (address = 0x15)
        4. 7.6.4.4  CH1VLEDOFF Measurement (address = 0x16)
        5. 7.6.4.5  CH2VIN Measurement (address = 0x17)
        6. 7.6.4.6  CH2VLED Measurement (address = 0x18)
        7. 7.6.4.7  CH2VLEDON Measurement (address = 0x19)
        8. 7.6.4.8  CH2VLEDOFF Measurement (address = 0x1A)
        9. 7.6.4.9  TEMPL Measurement (address = 0x1B)
        10. 7.6.4.10 TEMPH Measurement (address = 0x1C)
        11. 7.6.4.11 V5D Measurement (address = 0x1D)
      5. 7.6.5 Limp-Home Configuration and Command Registers
        1. 7.6.5.1  LHCFG1 Register (address = 0x1E) [reset =0x00]
        2. 7.6.5.2  LHCFG2 Register (address = 0x1F) [reset =0x00h]
        3. 7.6.5.3  LHIL Measurement (address = 0x20)
        4. 7.6.5.4  LHIH Measurement (address = 0x21)
        5. 7.6.5.5  LHIFILTL Register (address = 0x22)
        6. 7.6.5.6  LHIFILTH Register (address = 0x23)
        7. 7.6.5.7  LH1IADJL Register (address = 0x24) [reset = 0x00]
        8. 7.6.5.8  LH1IADJH Register (address = 0x25) [reset = 0x00]
        9. 7.6.5.9  LH2IADJL Register (address = 0x26) [reset = 0x00]
        10. 7.6.5.10 LH2IADJH Register (address = 0x27) [reset = 0x00]
        11. 7.6.5.11 LH1PWML Register (address = 0x28) [reset = 0x00]
        12. 7.6.5.12 LH1PWMH Register (address = 0x29) [reset = 0x00]
        13. 7.6.5.13 LH2PWML Register (address = 0x2A) [reset = 0x00]
        14. 7.6.5.14 LH2PWMH Register (address = 0x2B) [reset = 0x00]
        15. 7.6.5.15 LH1TON Register (address = 0x2C) [reset = 0x07]
        16. 7.6.5.16 LH2TON Register (address = 0x2D) [reset = 0x07]
      6. 7.6.6 RESET Register (address = 0x2E) (Write-Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Duty Cycle Consideration
      2. 8.1.2  Switching Frequency Selection
      3. 8.1.3  LED Current Set Point
      4. 8.1.4  Inductor Selection
      5. 8.1.5  Output Capacitor Selection
      6. 8.1.6  Input Capacitor Selection
      7. 8.1.7  Bootstrap Capacitor Selection
      8. 8.1.8  Compensation Capacitor Selection
      9. 8.1.9  Input Undervoltage Protection
      10. 8.1.10 CSN Protection Diode
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1 Calculating Duty Cycle
          2. 8.2.1.1.2 Calculating Minimum On-Time and Off-Time
          3. 8.2.1.1.3 Minimum Switching Frequency
          4. 8.2.1.1.4 LED Current Set Point
          5. 8.2.1.1.5 Inductor Selection
          6. 8.2.1.1.6 Output Capacitor Selection
          7. 8.2.1.1.7 Bootstrap Capacitor Selection
          8. 8.2.1.1.8 Compensation Capacitor Selection
          9. 8.2.1.1.9 External Channel Enable and PWM dimming
      2. 8.2.2 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Initialize Device without Watchdog timer
      2. 8.3.2 Initialize Device with Watchdog Timer
      3. 8.3.3 Limp-Home Mode
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
        1. 10.1.1.1 Ground Plane
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.13 Faults and Diagnostics

Table 7-1 summarizes the device behavior under fault conditions.

Table 7-1 Fault Description
FAULTDETECTIONDESCRIPTION
Thermal WarningTJ > TJ(LMT)Thermal warning (TW) bit is set in the STATUS3 register when the junction temperature exceeds the threshold programmed by TWLMT[9:2].
Thermal ProtectionTJ > 175°CEach channel is protected by an individual thermal sensor located close to the switching MOSFETs. The thermal protection is activated in the event the maximum MOSFET temperature exceeds the typical value of 175°C. The corresponding channel is forced into shutdown mode and the CHxTS bit is set in the STATUS2 register. This feature is designed to prevent overheating and damage to the internal switching MOSFETs.
SPI Error—A communication error is indicated by the SPE bit and it is set high. The device enters stand-alone mode or LIMP-HOME mode of operation when the watchdog timer duration expires (CMWTAP register) and the watchdog timeout event counter (CMWTO[1:0] in the STATUS3 register).
V5D Undervoltage LockoutV5D(RISE) < 4.1 VThe device enters the undervoltage lockout (UVLO). The switching operation is disabled, the COMP capacitor is discharged, and the digital logic is reset to default values. The power cycle (PC) bit is set in the STATUS3 register.
V5D(FALL) > 4 V
V5A Undervoltage LockoutV5A(RISE) < 4.1 VIn SLEEP mode, the internal V5A node is disconnected to reduce the current consumption. The switching operation is disabled and the COMP capacitor is discharged. The V5AUV bit is set in the STATUS3 register.
V5A(FALL) > 4 V
VINx Undervoltage LockoutVUDIMx < 1.12 VThe device disables switching operation for the corresponding channel. Switching is enabled when the input voltage rises above the turnon threshold, VIN(RISE).
BSTx Undervoltage LockoutVBSTx(RISE) > 3.14VThe device turns off the high-side MOSFET and turns on the low-side MOSFET for the corresponding channel. The CHxBSTUV bit is set in the STATUS2 register. Normal switching operation is resumed once the bootstrap voltage exceeds 2.95 V.
VBSTx(FALL) < 2.95 V
COMPx OvervoltageVCOMPx > 3.2 VThe CHxCOMPOV bit in the STATUS1 register is set to indicate that the COMP voltage exceeded the normal operating range. This information is provided for device diagnostics.
Short CHx OutputVCSNx < 2.45 VThe CHxSHORT bit is set in the STATUS1 register to indicate an output short circuit condition based on sensed CSNx voltage.
High-Side Switch Current LimitIHS > 2.7 AThe device turns off the high-side MOSFET and discharges the COMP capacitor when the drain current exceeds 2.7 A typical. The low-side switch is turned on to discharge the inductor and output capacitor. The CHxHSILIM bit is set in the STATUS1 register. The fault recovery is based on the device configuration.
Low-Side Switch Current LimitILS > 1.5 AThe device turns off both high-side and low-side MOSFETs and discharges the COMP capacitor when the drain current exceeds 1.5 A typical. The CHxLSILIM bit is set in the STATUS1 register. The fault recovery is based on the device configuration.
Minimum Off-Time—The CHxTOFFMIN bit is set in the STATUS2 register when the corresponding channel reaches the maximum possible duty cycle. This usually occurs during dropout condition or PWM dimming operation. The compensation network is disconnected from the output of the error amplifier to prevent COMP voltage from exceeding the normal operating range. Normal operation is resumed once the off-time increases above the minimum limit.

All the faults and diagnostics features, except V5D UVLO and VINx UVLO, have an associated Fault-Read bit in the STATUS1, STATUS2, and STATUS3 registers. Upon occurrence of a fault, the associated Fault-Read bit is set in the register map. Reading these registers clears the bits if the condition no longer exists. The clearing of the Fault-Read bits happens at the end of the SPI transfer read response, not at the end of the read command.

The TPS92520-Q1 can be configured to auto-restart or latch-off on detection of the thermal shutdown, high-side, or low-side current limit faults. The device enters the latched-off state when the bit associated with the fault and channel is set high in the SYSCFG2 register. This forces the device to disable the channel and remain off upon the detection of the fault condition. The channel can be turned back on by clearing the fault bit in STATUS1 and by re-setting the CHxEN bit in the SYSCFG1 register.

If the fault is configured as non-latched (the CHxTS, CHxHSILIMFL, or CHxLSILIMFL bit is set to 0 in the SYSCFG2 register), a restart sequence is initiated to attempt recovery from the fault condition. In the case of thermal shutdown fault, the restart is initiated after the MOSFET temperature decreases by the fixed hysteresis of 10°C. A soft-start sequence is initiated and switching operation is enabled. For a high-side or low-side current limit fault, a fixed timer is initiated on detection of the fault. The fault timer is programmable with a range of 3.6 ms to 28.8 ms by IFT[1:0] bits in SYSCFG2 register. A restart is initiated by the expiration of the fault timer and switching operation is enabled.

The TPS92520-Q1 logic has a communication watchdog timer that is based on the system clock (CLK). The watchdog timer is enabled by default upon power-up (the CMWEN bit is set to 1 in the SYSCFG1 register). The communications watchdog timer tap point is programmed by writing the desired value to the CMWTAP register.

The tap point defines the timing of the communication watchdog timer (a 25-bit counter). By default, the tap point is set to bit 24 corresponding to 1.67 s of duration. The communication watchdog monitors the status of SPI bus and defines the device operation in case of SPI communication error (SPE bit set to 1). See the Device Functional Modes for more details.

The high-side current limit, low-side current limit, and thermal protection faults force the FLT pin low when biased through an external resistor and connected to a 5-V supply. The FLT output can be used in conjunction with a microcontroller or system basis chip (SBC) as an interrupt and can be used to aid in fault diagnostics. Setting the FPINRST bit to one in SYSCFG1 register resets the FLT pin out when no active faults are detected by the device.

Table 7-2 Faults and Diagnostics Summary
LISTDESCRIPTIONFAULT OR DIAGNOSTICFAULT READ BITENABLE FAULT TIMERFLT INDICATIONENABLE LATCH
TWThermal WarningDiagnosticsYesNoNoNo
CHxTPThermal ProtectionFaultYesNoYesYes
VINx(UVLO)VIN Supply Undervoltage LockoutFaultNoNoNoNo
CHxBSTUVBST Supply Undervoltage LockoutFaultYesNoNoNo
CHxCOMPOVCOMP OvervoltageDiagnosticsYesNoNoNo
CHxSHORTShort Circuit DetectedDiagnosticsYesNoNoNo
CHxHSILIMHigh-side Current LimitFaultYesYesYesYes
CHxLSILIMLow-side Current LimitFaultYesYesYesYes
CHxTOFFMINMinimum Off TimeDiagnosticsYesNoNoNo
V5AUVV5A UndervoltageDiagnosticsYesNoNoNo
PCPower On Reset (Power Cycle)FaultYesNoYesYes
SPESPI Communication ErrorDiagnosticsYesNoNoNo
LHSWLimp-Home Mode (Communication Error)FaultYesNoNoNo