SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
Figure 7-34 shows the PWMDIV register. Table 7-21 describes the PWMDIV register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWMDIV[2:0] | ||||||
R-00000b | R/W-100b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 00000 | Reserved |
2-0 | PWMDIV[2:0] | R/W | 100 | This 3-bit value selects the clock divider for the internal PWM generator. The PWM clock is derived based on typical oscillator frequency of 10.8 MHz. 000 = Divide oscillator clock by 7 (fPWM = 1507 Hz). 001 = Divide oscillator clock by 8 (fPWM = 1318 Hz). 010 = Divide oscillator clock by 10 (fPWM = 1055 Hz). 011 = Divide oscillator clock by 12 (fPWM = 879 Hz). 100 = Divide oscillator clock by 16 (fPWM = 659 Hz). 101 = Divide oscillator clock by 24 (fPWM = 439 Hz). 110 = Divide oscillator clock by 49 (fPWM = 215 Hz). 111 = Divide oscillator clock by 98 (fPWM = 108 Hz). |