In earlier sections of this report, it was
shown that as PWM frequency increases the effects of PWD on load power increases causing
significant divergence from the calculated ideal power.
A high side switch's finite slew rate
introduces additional challenges that deviates true load power from an ideal case.
Unlike PWD, which can either increase or decrease delivered load power, finite slew-rate
always results in reduced load power compared to an ideal high side switch as
the rise times reduce the time when the full input voltage is present across the load.
As frequency increases, the rise and fall times account for more and more of the output
ON pulse.
Figure 3-8 defines timing parameters used for analysis.
tON is the total duration of the ON cycle pulse.
- t'ON
is the total duration where output is at final voltage
- tpw(OUT)
is the output pulse width
- trise,fall are rise
and fall times calculated from device slew rate, such that
Equation 28.
Equation 28.
The average dissipated power in a resistor is
R·IAVG2. When considering the slew rate,
voltage becomes a linear function of time during rise and fall times. By decomposing the
resistor power into the rising, falling, and steady periods of output voltage, we can
calculate average load power for an arbitrary resistor with a severely distorted output
pulse.
Equation 28. Equation 28.
Splitting up the ON cycle waveform yields
Equation 28. Even if rise and fall waveforms were complex, it would not be a good
use of time to start integrating at this point. As we are assuming the rise and fall
periods are linear (constant slew rates), our output waveform is trapezoidal and the
power calculation simplifies.
Equation 28. , where
Vvs is the supply voltage. This can be further
simplified to:
Equation 28.
As slew rates increase, power dissipated in the resistive load
is reduced. At the point where the output only reaches
Vvs
output power is halved. If frequency is increased further than this point, slew rates
will further reduce power as the output will never reach
Vvs.