SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

5.2 Updating the Frequency Selection

The buck frequency selection is protected by bit 3 in register address 0x18 of page 1. The buck frequency cannot be updated until this bit is set and the bit cannot be set unless the NVM is unlocked. Once the frequency update is made the bit must be cleared. Typically this is accomplished in the normal program flow when register 0x18 of page 1 is written.