SLVAFT6 September   2024 TPS23521 , TPS23523 , TPS23525

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Existing Design and Challenges
  6. 3Negative Hot-Swap Controller – TPS2352x
  7. 4Output Voltage Clamping with TPS2352x
  8. 5Design Procedure and Implementation
    1. 5.1 Configuring the Current Limit Switch-Over Threshold for TPS2352x
    2. 5.2 Feedback and Control Loop Response
    3. 5.3 Powering the Feedback Amplifier
    4. 5.4 Noise Immunity
  9. 6Test Results
    1. 6.1 Startup
    2. 6.2 NEBS Transient Response
  10. 7Summary
  11. 8References

6.1 Startup

Figure 6-1 shows a successful startup of the system at NO LOAD condition. A voltage of 48V is applied across the system input. The voltage at the GATE of the FET starts to rise after an insertion delay of 32ms. The Vgs-th of the selected FET is 2.6V post which we can see that the Vds starts to come down and the Vout starts to rise and follows the input.

Startup Waveform in the Proposed DesignFigure 6-1 Startup Waveform in the Proposed Design