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  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to linear regulator turn-on time
  5. 2What impacts the LDO rise time?
    1. 2.1 Simple Use Cases
      1. 2.1.1 Case 1: LDO with an NR filter but without CFF capacitance
      2. 2.1.2 Case 2: NR filter with a CFF capacitance
      3. 2.1.3 Fast-charge circuitry
      4. 2.1.4 Non-ideal LDO behavior
        1. 2.1.4.1 Applied voltage bias
        2. 2.1.4.2 Fast charge current tolerance
        3. 2.1.4.3 Internal error amplifier offset voltage
        4. 2.1.4.4 Temperature impacts the fast-charge current source
        5. 2.1.4.5 Error amplifier common mode voltage
        6. 2.1.4.6 Reference voltage (VREF) ramp time dominates the turn-on time
        7. 2.1.4.7 Start-up during dropout mode
        8. 2.1.4.8 Large values of COUT induce internal current limit
        9. 2.1.4.9 Limitations of large-signal LDO bandwidth
    2. 2.2 Specific Use Cases and Examples
      1. 2.2.1 Case 3: Precision voltage reference with RNR/SS and parallel IFC fast charge
      2. 2.2.2 Case 4: Precision voltage reference with IFC fast charge and no RNR/SS
      3. 2.2.3 Case 5: Precision current reference
      4. 2.2.4 Case 6: Soft-start timing
  6. 3System Considerations
    1. 3.1 Inrush current calculation
    2. 3.2 Inrush current analysis
    3. 3.3 Maximum slew rate
  7. 4LDO regulators referenced in this paper
  8. 5Conclusion
  9. 6References

2.1.4.1 Applied voltage bias

In general, applied voltage bias has a minor impact to the turn-on time. Changes to the effective capacitance of modern ceramic capacitors due to voltage bias require significant amounts of time [20]. The typical LDO regulator turn-on times are too short to meaningfully impact CNR/SS and CFF capacitance due to the change in voltage bias. Exceptions to this generalization are rare use cases where the LDO regulator is purposely designed for a long turn-on time while simultaneously operating without current limit engaged.