SLVAFX0 October   2024 TLV702 , TLV703 , TLV755P , TPS74401 , TPS7A13 , TPS7A14 , TPS7A20 , TPS7A21 , TPS7A49 , TPS7A52 , TPS7A53 , TPS7A53B , TPS7A54 , TPS7A57 , TPS7A74 , TPS7A83A , TPS7A84A , TPS7A85A , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7H1111-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to linear regulator turn-on time
  5. 2What impacts the LDO rise time?
    1. 2.1 Simple Use Cases
      1. 2.1.1 Case 1: LDO with an NR filter but without CFF capacitance
      2. 2.1.2 Case 2: NR filter with a CFF capacitance
      3. 2.1.3 Fast-charge circuitry
      4. 2.1.4 Non-ideal LDO behavior
        1. 2.1.4.1 Applied voltage bias
        2. 2.1.4.2 Fast charge current tolerance
        3. 2.1.4.3 Internal error amplifier offset voltage
        4. 2.1.4.4 Temperature impacts the fast-charge current source
        5. 2.1.4.5 Error amplifier common mode voltage
        6. 2.1.4.6 Reference voltage (VREF) ramp time dominates the turn-on time
        7. 2.1.4.7 Start-up during dropout mode
        8. 2.1.4.8 Large values of COUT induce internal current limit
        9. 2.1.4.9 Limitations of large-signal LDO bandwidth
    2. 2.2 Specific Use Cases and Examples
      1. 2.2.1 Case 3: Precision voltage reference with RNR/SS and parallel IFC fast charge
      2. 2.2.2 Case 4: Precision voltage reference with IFC fast charge and no RNR/SS
      3. 2.2.3 Case 5: Precision current reference
      4. 2.2.4 Case 6: Soft-start timing
  6. 3System Considerations
    1. 3.1 Inrush current calculation
    2. 3.2 Inrush current analysis
    3. 3.3 Maximum slew rate
  7. 4LDO regulators referenced in this paper
  8. 5Conclusion
  9. 6References

1 Introduction to linear regulator turn-on time

The turn-on time (tON) for an LDO regulator is a summation of the delay time (tD) and the rise time (tR) (see Equation 1 and Figure 1-1). The delay time is defined as the fixed time delay from when the output voltage can start to increase with respect to an external stimulus, to when the output voltage actually begins to increase. If the LDO regulator has an enable pin, the external stimulus typically occurs when the enable voltage toggles to turn on the LDO regulator. This behavior assumes that the input voltage has already been applied to the input of the LDO regulator. For LDO regulators without an EN pin, the input voltage acts as the external stimulus.

TPS7A20, TPS7A21, TPS7A13, TPS7A14, TPS7A49, TPS7A91, TPS7A92, TLV702, TLV703, TLV755P, TPS7A52, TPS7A53, TPS7A53B, TPS7A54, TPS7A83A, TPS7A84A, TPS7A85A, TPS7A57, TPS7A94, TPS7A96, TPS7H1111-SP, TPS74401, TPS7A74, TPS74701, TPS74801, TPS74901 Total turn-on time vs input voltage Figure 1-1 Total turn-on time vs input voltage
A. Minimum VOUT regulation
Equation 1. t O N = t D + t R

Delay time for an LDO regulator is usually small compared to the rise time. Delay times result from how quickly the device can energize internal circuitry to begin increasing the output voltage. The LDO regulator data sheet gives the best estimate of the delay time because after the device is enabled, external circuitry has little influence on the delay time. The rise time is the time to increase the output voltage from 0V to the minimum regulation. Each application requires unique regulation so the minimum regulation point is application specific. For example, one design may allow a tolerance of ± 3% while another design may allow a tolerance of ± 5%. Thus, the turn-on time is faster for a design with wider tolerance requirements.