SLVAFX0 October   2024 TLV702 , TLV703 , TLV755P , TPS74401 , TPS7A13 , TPS7A14 , TPS7A20 , TPS7A21 , TPS7A49 , TPS7A52 , TPS7A53 , TPS7A53B , TPS7A54 , TPS7A57 , TPS7A74 , TPS7A83A , TPS7A84A , TPS7A85A , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7H1111-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to linear regulator turn-on time
  5. 2What impacts the LDO rise time?
    1. 2.1 Simple Use Cases
      1. 2.1.1 Case 1: LDO with an NR filter but without CFF capacitance
      2. 2.1.2 Case 2: NR filter with a CFF capacitance
      3. 2.1.3 Fast-charge circuitry
      4. 2.1.4 Non-ideal LDO behavior
        1. 2.1.4.1 Applied voltage bias
        2. 2.1.4.2 Fast charge current tolerance
        3. 2.1.4.3 Internal error amplifier offset voltage
        4. 2.1.4.4 Temperature impacts the fast-charge current source
        5. 2.1.4.5 Error amplifier common mode voltage
        6. 2.1.4.6 Reference voltage (VREF) ramp time dominates the turn-on time
        7. 2.1.4.7 Start-up during dropout mode
        8. 2.1.4.8 Large values of COUT induce internal current limit
        9. 2.1.4.9 Limitations of large-signal LDO bandwidth
    2. 2.2 Specific Use Cases and Examples
      1. 2.2.1 Case 3: Precision voltage reference with RNR/SS and parallel IFC fast charge
      2. 2.2.2 Case 4: Precision voltage reference with IFC fast charge and no RNR/SS
      3. 2.2.3 Case 5: Precision current reference
      4. 2.2.4 Case 6: Soft-start timing
  6. 3System Considerations
    1. 3.1 Inrush current calculation
    2. 3.2 Inrush current analysis
    3. 3.3 Maximum slew rate
  7. 4LDO regulators referenced in this paper
  8. 5Conclusion
  9. 6References

3.3 Maximum slew rate

In some applications the LDO regulator must limit the slew rate during the turn-on period [17] , [18], and [19], and the most desirable way to achieve this requirement is to adjust the CNR/SS or CFF capacitance. These slew rate requirements may be enforced across a narrow range of turn on, such as between 2V and 4V of a 5V output, or across the entire voltage range from 0V to steady state. In general, it may be more challenging to meet these requirements using a device with an exponentially rising output as shown in Figure 3-4 than a linear ramp as shown in Figure 3-3. To slow down a fixed output LDO regulator where the NR filter and feedback resistors are internal to the device, the only option remaining is to increase the output capacitance, COUT such that the current limit loop engages approximately 20µs to 50µs into the turn-on period.

TPS7A20, TPS7A21, TPS7A13, TPS7A14, TPS7A49, TPS7A91, TPS7A92, TLV702, TLV703, TLV755P, TPS7A52, TPS7A53, TPS7A53B, TPS7A54, TPS7A83A, TPS7A84A, TPS7A85A, TPS7A57, TPS7A94, TPS7A96, TPS7H1111-SP, TPS74401, TPS7A74, TPS74701, TPS74801, TPS74901 TPS7A20 output voltage slew rate Figure 3-4 TPS7A20 output voltage slew rate