SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

7.4.3 JESD204B Modes

The ADC12DJ3200QML-SP can be programmed as a single-channel or dual-channel ADC, with or without decimation, and a number JESD204B output formats. Table 7-16 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.

CAUTION:

Powering down high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended times can damage the output serializers, especially at high data rates. For information regarding reliable serializer operation, see the Power-Down Modes section.

Table 7-16 ADC12DJ3200QML-SP Operating Mode Configuration Parameters
PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDVALUE
JMODEJESD204B operating mode, automatically derives the rest of the JESD204B parameters, single-channel or dual-channel mode and the decimation factorUser configuredSet by JMODE (see the JESD204B mode register)
DDecimation factorDerivedSee Table 7-18
DES1 = single-channel mode, 0 = dual-channel modeDerivedSee Table 7-18
RNumber of bits transmitted per lane per DEVCLK cycle. The JESD204B line rate is the DEVCLK frequency times R. This parameter sets the SerDes PLL multiplication factor or controls bypassing of the SerDes PLL.DerivedSee Table 7-18
LinksNumber of JESD204B links usedDerivedSee Table 7-18
KNumber of frames per multiframeUser configuredSet by KM1 (see the JESD204B K parameter register), see the allowed values in Table 7-18

There are a number of parameters required to define the JESD204B format, all of which are sent across the link during the initial lane alignment sequence. In the ADC12DJ3200QML-SP, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 7-17 describes these parameters.

Table 7-17 JESD204B Initial Lane Alignment Sequence Parameters
PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDVALUE
ADJCNTLMFC adjustment amount (not applicable)DerivedAlways 0
ADJDIRLMFC adjustment direction (not applicable)DerivedAlways 0
BIDBank IDDerivedAlways 0
CFNumber of control words per frameDerivedAlways 0
CSControl bits per sampleDerivedAlways set to 0 in ILAS, see Table 7-18 for actual usage
DIDDevice identifier, used to identify the linkUser configuredSet by DID (see the JESD204B DID parameter register), see Table 7-19
FNumber of octets (bytes) per frame (per lane)DerivedSee Table 7-18
HDHigh-density format (samples split between lanes)DerivedAlways 0
JESDVJESD204 standard revisionDerivedAlways 1
KNumber of frames per multiframeUser configuredSet by the KM1 register, see the JESD204B K parameter register
LNumber of serial output lanes per linkDerivedSee Table 7-18
LIDLane identifier for each laneDerivedSee Table 7-19
MNumber of converters used to determine lane bit packing; may not match number of ADC channels in the deviceDerivedSee Table 7-18
NSample resolution (before adding control and tail bits)DerivedSee Table 7-18
N'Bits per sample after adding control and tail bitsDerivedSee Table 7-18
SNumber of samples per converter (M) per frameDerivedSee Table 7-18
SCRScrambler enabledUser configuredSet by the JESD204B control register
SUBCLASSVDevice subclass versionDerivedAlways 1
RES1Reserved field 1DerivedAlways 0
RES2Reserved field 2DerivedAlways 0
CHKSUMChecksum for ILAS checking (sum of all above parameters modulo 256)DerivedComputed based on parameters in this table

Configuring the ADC12DJ3200QML-SP is made easy by using a single configuration parameter called JMODE (see the JESD204B mode register). Using Table 7-18, the correct JMODE value can be found for the desired operating mode. The modes listed in Table 7-18 are the only available operating modes. This table also gives a range and allowable step size for the K parameter (set by KM1, see the JESD204B K parameter register), which sets the multiframe length in number of frames.

Table 7-18 ADC12DJ3200QML-SP Operating Modes
ADC12DJ3200QML-SP OPERATING MODE USER-SPECIFIED PARAMETER DERIVED PARAMETERS INPUT CLOCK RANGE (MHz)
JMODE K
[Min:Step:Max]		 D DES Links N CS N’ L
(Per Link)		 M
(Per Link)		 F S R
(Fbit / Fclk)
12-bit, single-channel, 8 lanes 0 3:1:32 1 1 2 12 0 12 4 4(1) 8 5 4 800-3200
12-bit, single-channel, 16 lanes 1 3:1:32 1 1 2 12 0 12 8 8(1) 8 5 2 800-3200
12-bit, dual-channel, 8 lanes 2 3:1:32 1 0 2 12 0 12 4 4(1) 8 5 4 800-3200
12-bit, dual-channel, 16 lanes 3 3:1:32 1 0 2 12 0 12 8 8(1) 8 5 2 800-3200
8-bit, single-channel, 4 lanes 4 18:2:32 1 1 2 8 0 8 2 1 1 2 5 800-2560
8-bit, single-channel, 8 lanes 5 18:2:32 1 1 2 8 0 8 4 1 1 4 2.5 800-3200
8-bit, dual-channel, 4 lanes 6 18:2:32 1 0 2 8 0 8 2 1 1 2 5 800-2560
8-bit, dual-channel, 8 lanes 7 18:2:32 1 0 2 8 0 8 4 1 1 4 2.5 800-3200
Reserved 8 — — — — — — — — — — — — —
15-bit, real data, decimate-by-2, 8 lanes 9 9:1:32 2 0 2 15 1(2) 16 4 1 2 4 2.5 800-3200
15-bit, decimate-by-4, 4 lanes 10 9:1:32 4 0 2 15 1(2) 16 2 2 2 1 5 800-2560
15-bit, decimate-by-4, 8 lanes 11 9:1:32 4 0 2 15 1(2) 16 4 2 2 2 2.5 800-3200
12-bit, decimate-by-4, 16 lanes 12 3:1:32 4 0 2 12 0 12 8 8(1) 8 5 1 1000-3200
15-bit, decimate-by-8, 2 lanes 13 5:1:32 8 0 2 15 1(2) 16 1 2 4 1 5 800-2560
15-bit, decimate-by-8, 4 lanes 14 9:1:32 8 0 2 15 1(2) 16 2 2 2 1 2.5 800-3200
15-bit, decimate-by-16, 1 lane 15 3:1:32 16 0 1 15 1(2) 16 1 4 8 1 5 800-2560
15-bit, decimate-by-16, 2 lanes 16 5:1:32 16 0 2 15 1(2) 16 1 2 4 1 2.5 800-3200
8-bit, single-channel, 16 lanes 17 18:2:32 1 1 2 8 0 8 8 1 1 8 1.25 800-3200
8-bit, dual-channel, 16 lanes 18 18:2:32 1 0 2 8 0 8 8 1 1 8 1.25 800-3200
(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see Table 7-20 to Table 7-37 for more details.
(2) CS is always reported as 0 in the initial lane alignment sequence (ILAS) for the ADC12DJ3200QML-SP.

The ADC12DJ3200QML-SP has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204B links. Most operating modes use two links with up to eight lanes per link. The lanes and their derived configuration parameters are described in Table 7-19. For a specified JMODE, the lowest indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down. Always route the lowest indexed lanes to the logic device.

Table 7-19 ADC12DJ3200QML-SP Lane Assignment and Parameters
DEVICE PIN DESIGNATIONLINKDID (User Configured)LID (Derived)
DA0±ASet by DID (see theJESD204B DID parameter register), the effective DID is equal to the DID register setting (DID)0
DA1±1
DA2±2
DA3±3
DA4±4
DA5±5
DA6±6
DA7±7
DB0±BSet by DID (see theJESD204B DID parameter register), the effective DID is equal to the DID register setting plus 1 (DID+1)0
DB1±1
DB2±2
DB3±3
DB4±4
DB5±5
DB6±6
DB7±7