SLVUBT8B November   2020  – June 2022 LP8764-Q1 , TPS6594-Q1

 

  1.   Scalable PMIC's GUI User’s Guide
  2.   Trademarks
  3. 1 Introduction
  4. 2 Supported Features
  5. 3 Revisions
  6. 4 Overview
  7. 5 Getting Started
    1. 5.1 Finding the GUI
    2. 5.2 Downloading the Required Software
    3. 5.3 Launching the GUI
    4. 5.4 Connecting to a PMIC
  8. 6 Quick-start Page
    1. 6.1 Device Scan Results
    2. 6.2 Configuration and Monitoring
      1. 6.2.1 System Info
      2. 6.2.2 BUCK
      3. 6.2.3 LDO
      4. 6.2.4 GPIO
      5. 6.2.5 Interrupts
      6. 6.2.6 Miscellaneous Settings
      7. 6.2.7 Advanced
  9. 7 Register Map Page
  10. 8 NVM Configuration Page
    1. 8.1 Creating a Custom Configuration
      1. 8.1.1 Static Configuration
      2. 8.1.2 Pre-Configurable Mission States (PFSM)
        1. 8.1.2.1 Creating a State Diagram
        2. 8.1.2.2 Global Settings
        3. 8.1.2.3 Power Sequence
          1. 8.1.2.3.1 Power Sequence Resources and Commands
          2. 8.1.2.3.2 Sub-sequences
          3. 8.1.2.3.3 Power Sequence Editing Tools
        4. 8.1.2.4 Trigger Settings
        5. 8.1.2.5 Trigger Priority List
        6. 8.1.2.6 PFSM Validation
    2. 8.2 Program
      1. 8.2.1 Program an Existing NVM Configuration
      2. 8.2.2 NVM Configuration Special Use Case: Changing the Communication Interface
      3. 8.2.3 Lock Option During NVM Programming
  11. 9 NVM Validation Page
  12. 10Watchdog Page
  13. 11Additional Resources
  14. 12Appendix A: Troubleshooting
    1. 12.1 Hardware Platform Not Recognized
    2. 12.2 PMIC Device Not Found
    3. 12.3 I2C2 is configured but not connected
  15. 13Appendix B: Advanced Topics
    1. 13.1 Scripting Window
  16. 14Appendix C: Known Limitations
  17. 15Appendix D: Migration Topics
    1. 15.1 Migrating from LP8764-Q1 PG1.0 to PG2.0
    2. 15.2 Update the PFSM to Include the PFSM_START State
    3. 15.3 Update Timing Delays
    4. 15.4 Update Trigger Priority and Settings
  18. 16Revision History

5.4 Connecting to a PMIC

The GUI and AEVM support both I2C and SPI with and without CRC. As mentioned previously, when entering the Register Map and Quick-start pages, the GUI will attempt to connect to any device with a non-CRC I2C interface at address 0x48. If an alternate address or configuration is needed, then the Device Settings window is provided to change the settings, as shown in Figure 5-7. This window can also be accessed in the drop-down menu below Options.

GUID-20200831-CA0I-ZVNR-PDJS-XXRSDQ80KHKJ-low.png Figure 5-7 Device Settings From Options Tab
GUID-20200813-CA0I-ZVRN-WVJP-VXXFL1CBLF8T-low.png Figure 5-8 Device Interface Settings

As shown in Figure 5-8, options are provided to select the device as well as the interface.

Select Device

The device selection will determine the register interpretation of data written to and read from the PMIC. Failure to select the correct device can result in erroneous data being written to the PMIC or data read from the PMIC to be misinterpreted.

I2C

The I2C1 address selection is limited to valid page 0 addresses of the PMIC. Once the I2C1 address is specified, the GUI will automatically determine the addresses for pages 1-4 as well as determine if the physical I2C2 interface for page 4 is to be used.

SPI

Similar to the I2C implementation, the GUI will automatically update the page information during communication.

The latest AEVM controller firmware will support multi-PMIC operation by providing individual chip select (CS) control. As shown in Figure 5-9, up to 6 PMICs can be cascaded in a primary/secondary configuration and communication with each device is controlled by the chip selection. Table 5-1 shows the relationship with the AEVM GPIO.

Figure 5-9 SPI Multi-PMIC Chip Select
Table 5-1 Chip Select Representation on AEVM
Chip Select AEVM Port
Multi-PMIC is not selected PD2, QSSI module CS is used
1 PD2, QSSI module CS is used
2 PD7
3 PC7
4 PC6
5 PC5
6 PC4

Updating the Interface

In addition to the Option tab at the top of the GUI, in the Quick-start, Register Map, and Watchdog pages, there is a device settings bar that shows the current interface selection. Clicking the gear icon within the bar also opens the Device Settings window. In the NVM Configuration and NVM Validation pages, the interface selection is provided within the page. Please refer to those sections for more details.

GUID-20200831-CA0I-JL8B-TDTB-1F6M4KBN2CKX-low.png Figure 5-10 Device Settings Bar
Note:

Connecting to a device is not required to access the GUI pages. Specifically, connecting to a device is not required to create an NVM configuration as described in section Section 8