SLVUBY7A October 2020 – October 2022 DRA821U , DRA821U-Q1 , LP8764-Q1 , TPS6594-Q1
This user’s guide can be used as a guide for integrating the TPS6594-Q1 and LP8764-Q1 power management integrated circuits (PMICs) into a system powering the DRA821 processor.
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This user’s guide defines the power distribution network (PDN) between the TPS6594-Q1 and LP8764-Q1 devices and the DRA821 processor. This document describes the platform power resource connections, digital control connections, and PMIC sequencing settings to support the different processor state transitions. The PMIC default non-volatile memory (NVM) settings, internal state transitions, and power sequences are also defined in this document. This user's guide does not provide information about the electrical characteristics, external components, package, or the functionality of the PMICs or processor. For such information and the full register maps, refer to the data sheet for each device. In the event of any inconsistency between the official specification and any user's guide, application report, or other referenced material, the data sheet specification is the definitive source.