SLVUBY7A October   2020  – October 2022 DRA821U , DRA821U-Q1 , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

5.7 Finite State Machine (FSM) Settings

These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default trigger for each system-level state is described. All these settings can be changed though I2C after startup.

Table 5-8 FSM NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
RAIL_SEL_1 BUCK1_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK2_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK3_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
BUCK4_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
RAIL_SEL_2 BUCK5_GRP_SEL 0x2 SOC rail group
LDO1_GRP_SEL 0x1 MCU rail group
LDO2_GRP_SEL 0x2 SOC rail group
LDO3_GRP_SEL 0x1 MCU rail group
RAIL_SEL_3 VMON2_GRP_SEL 0x0 No group assigned
VMON1_GRP_SEL 0x0 No group assigned
LDO4_GRP_SEL 0x2 SOC rail group
VCCA_GRP_SEL 0x1 MCU rail group 0x1 MCU rail group
FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x2 MCU power error 0x2 MCU power error
SOC_RAIL_TRIG 0x3 SOC power error 0x3 SOC power error
OTHER_RAIL_TRIG 0x3 SOC power error 0x3 SOC power error
SEVERE_ERR_TRIG 0x0 Immediate shutdown 0x0 Immediate shutdown
FSM_TRIG_SEL_2 MODERATE_ERR_TRIG 0x1 Orderly shutdown 0x1 Orderly shutdown