SLVUBY7A October   2020  – October 2022 DRA821U , DRA821U-Q1 , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

3 Processor Connections

This section details how the TPS6594-Q1 and LP8764-Q1 power resources and GPIO signals are connected to the processor and other peripheral components to support the PDN use case.

Figure 3-1 shows the detailed power mapping between the processor and the TPS6594-Q1 and LP8764-Q1 PMICs. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must be supplied after VCCA. In this configuration, VIO_IN is supplied by the load switch that also supplies the VDDSHVx_MCU voltage domain of the processor to allow the digital components of the PMIC devices (such as GPIOs) to remain supplied in MCU-only mode. Additionally, by controlling VIO_IN of both PMICs through this load switch, the system can also reduce power consumption in GPIO Retention or DDR Retention modes, since the load switch is disabled.

This PDN supports the use of either a single dual load switch (TPS22966-Q1) with an AEC-100 Grade 2 (-40 to +105°C) temperature rating or two single load switches (TPS22965-Q1) with an AEC-100 Grade 1 (-40 to +125°C) rating if a higher ambient temperature range is desired. The PDN diagrams of this section also include a few optional discrete power components to support additional system functions that may be needed. The TLV70033-Q1 LDO is used to support compliant USB data eye performance by supplying a low noise 3.3 V for USB 2.0 interface integration. The TLV70018-Q1 LDO is available to support on-board EFUSE programming on high security SoC PNs. Alternative LDOs can be chosen for SD card dual-voltage I/O support (3.3 V and 1.8 V), TLV7103318-Q1 dual-voltage LDO can be used to enable compliant, dual voltage, high-speed SD card operations.

Figure 3-1 TPS6594-Q1 and LP8764-Q1 Power Connections

The power resource assignments shown in Figure 3-1 enable the support for different processor low-power modes, including MCU-only mode, GPIO Retention, and DDR Retention. Please use Table 3-1 as a guide to understand which power resources are required to support different system features. If the system feature listed is not required, the power resource connection can be removed.

Table 3-1 Power Resources by System Power States
DevicePMIC ResourceProcessor DomainsPower States
Active SoCMCU - onlyGPIO RetentionDDR Retention
TPS6594-Q1BUCK1VDDA_xRequiredRequired
BUCK2VDDSHVx_MCU (1.8V)RequiredRequired
BUCK3VDD_MCU, VDDAR_MCURequiredRequired
BUCK4VDDS_DDR_BIAS, VDDS_DDR_IORequiredRequired
BUCK5VDDA_1P8_PHYsRequired
LDO1N/ARequiredRequired
LDO2VDDA_0P8_PLLs/DLLsRequired
LDO3VDD_WAKE0RequiredRequired
LDO4VDDA_1P8_PLLsRequired
LP8764-Q1BUCK1VDD_CPURequired
BUCK2VDDAR_CPU/CORERequired
BUCK3VDD_CORE, VDDA_0P8_PHYsRequired
BUCK4VDDS_MMC0Required
TPS22965-Q1Load SwitchVDDSHVx_MCU (3.3 V)RequiredRequired
TPS22966-Q1Load Switch 1VDDSHV0(1)Required
Load Switch 2VDDSHV2Required
(1) VDDSHV5 can also be powered by this rail if an SD card is not required in the system.

Figure 3-2 shows the digital control signal mapping between the processor and the PMIC devices. For the two PMIC devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication channel. The SPMI bus allows the TPS6594-Q1 and LP8764-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the TPS6594-Q1 and GPIO_8 and GPIO_9 pins on LP8764-Q1 are assigned for this functionality. In addition, the LDOVINT pin of the primary PMIC must be connected to the ENABLE input (GPIO_4 of LP8764-Q1) of the secondary PMIC to correctly initiate the PFSM.

Other digital connections from the TPS6594-Q1 devices to the processor allow support for error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

To support DDR retention low power mode, the following PMIC GPIO functions are required:

  1. GPIO_2 and GPIO_3 of LP8764-Q1 connected to an external, low voltage latch to create a sustained control signal to DDR_RET of the processor. The latch is needed since the PMIC VIO_IN power rail supplying GPIO_2 and 3 is disabled during DDR Retention state.
  2. Sustained GPIO_9 of TPS6594-Q1 connected to the enable input of a 3.3V in-line load switch to the MCU.
  3. Sustained GPIO_4 of TPS6594-Q1 with NVM default function set as LP_WKUP1 and mask bit set high to avoid false triggering until CAN wakeup signal is armed. SW must properly arm CAN PHY so that wakeup signal is set high and unmask GPIO_4 before entering GPIO Retention state.
GPIO_4 of TPS6594-Q1 is powered by the VRTC internal voltage domain of the PMIC. The LDOVRTC regulator supplies always-on functions, such as the wake-up function of GPIO_4. This enables GPIO_4 to be used as a wake-up source in LP_STANDBY when LDO_VINT is turned off.

To support GPIO retention low power mode, the following PMIC GPIO functions are required:

  1. Sustained GPIO_7 of LP8764-Q1 connected to the enable input of an in-line load switch to control the 3.3 V GPIO retention domain.

Additional digital options also include GPIO_10 of TPS6594-Q1, which can be configured by software as a 32 kHz clock output for the processor oscillator input (LFOSC ). There is also the option to disable the watchdog timer using hardware, by pulling GPIO_8 of TPS6594-Q1 high. Lastly, GPIO_1 of LP8764-Q1 is included in the power up sequence to enable external regulators, for options such as DDR I/O.

Figure 3-2 TPS6594-Q1 and LP8764-Q1 Digital Connections

The digital connections shown in Figure 3-2 allow system features including MCU-only mode, GPIO retention mode, DDR retention mode, and functional safety systems capable of supporting up to ASIL-D. Please use Table 3-2 as a guide to understand GPIO assignments required for these features. If the feature listed is not required, the digital connection can be removed. For details on how functional safety related connections help achieve functional safety system-level goals, see Section 4.

Table 3-2 Digital Connections by System Feature
DevicePMIC Digital SignalSystem Digital SignalSystem Features
Active SoCFunctional SafetyMCU - onlyGPIO RetentionDDR Retention
TPS6594-Q1nPWRON/ ENABLESystem ON RequestRequired
INT(1)Safety MCU GPIORequired
nRSTOUT(1)MCU_PORzRequiredRequired
SCL_I2C1WKUP_I2C0_SCLRequired
SDA_I2C1WKUP_I2C0_SDARequired
GPIO_1MCU_I2C0_SCLRequired
GPIO_2MCU_I2C0_SCLRequired
GPIO_3SOC_SAFETY_ERRORnOptional
GPIO_4(2)CAN WakeupRequiredRequired
GPIO_5PMIC SPMI CLKRequired
GPIO_6PMIC SPMI DATARequired
GPIO_7MCU_SAFETY_ERRORnOptional
GPIO_8 (5)Disable Watchdog(3)(3)
GPIO_9ENABLE MCU I/ORequired
GPIO_10(4)WKUP_LFOSC0Required
GPIO_11(1)SOC_PORzRequiredRequired
LP8764-Q1INT(1)Safety MCU GPIORequired
SCL_I2C1WKUP_I2C0_SCLRequired
SDA_I2C1WKUP_I2C0_SDARequired
GPIO_1Enable DDR I/O (Optional)
GPIO_2(5)External Latch Data InputRequired
GPIO_3(5)External Latch Clock InputRequired
GPIO_4TPS6594-Q1 LDOVINTRequired
GPIO_5(5)Enable EFUSE
GPIO_6 (5)N/A
GPIO_7EN_GPIO_RETRequiredRequired
GPIO_8PMIC SPMI CLKRequired
GPIO_9PMIC SPMI DATARequired
GPIO_10Enable Main I/ORequiredRequiredRequired
(1) This pin is open-drain to enable voltage translation to correct voltage level for processor interface.
(2) Software must unmask GPIO_4 before the system expects to trigger a wakeup on this pin.
(3) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(4) GPIO_10 is set as a general purpose input (GPI) by default to allow processor to boot up before sourcing the 32 kHz to the processor, since both bootmode and low frequency clock inputs to the processor utilize the same pin.
(5) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if desired.