SLVUC32B June   2021  – February 2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 To Suspend-to-RAM (TO_S2R)
  8. 7Impact of NVM Changes
  9. 8References
  10. 9Revision History

6.2 PFSM Triggers

As shown in Figure 6-1, there are various triggers that can enable a state transition between configured states. Table 6-1 describes each trigger and its associated state transition from highest priority (Immediate Shutdown) to lowest priority (I2C_3). Active triggers of higher priority block triggers of lower priority and the associated sequence.

Table 6-1 State Transition Triggers
ID Trigger Immediate (IMM) REENTERANT PFSM Current State PFSM Destination State Power Sequence or Function Executed
0 Immediate Shutdown True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE_SEVERE
1 MCU Power Error True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE
2(7) Orderly Shutdown True False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM SAFE(1) TO_SAFE_ORDERLY
4 OFF Request False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM STANDBY(2) TO_STANDBY
5 WDOG Error False True ACTIVE ACTIVE ACTIVE_TO_WARM
6 ESM MCU Error False True ACTIVE ACTIVE
7 ESM SOC Error False True ACTIVE ACTIVE ESM_SOC_ERROR
8 WDOG Error False True MCU ONLY MCU ONLY MCU_TO_WARM
9 ESM MCU Error False True MCU ONLY MCU ONLY
10 SOC Power Error False False ACTIVE MCU ONLY(8) PWR_SOC_ERR
11 I2C_1 bit is high(3) False True ACTIVE, MCU ONLY No State Change Execute RUNTIME BIST
12 I2C_2 bit is high(3) False True ACTIVE, MCU ONLY No State Change Enable I2C CRC on I2C1 and I2C2 on all devices.(4)
13 GPIO Falling Edge(1) False False ACTIVE No State Change TPS65941111-Q1 LDO1 output is 3.3 V in BYPASS mode
14 GPIO2 Rising Edge(1) False False ACTIVE No State Change TPS65941111-Q1 LDO1 output is 1.8 V in LDO mode
15 ON Request False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE TO_ACTIVE
16 WKUP1 goes high False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE
17 NSLEEP1 and NSLEEP2 are high(5) False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM ACTIVE
18 MCU ON Request False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM MCU ONLY TO_MCU
19 WKUP2 goes high False False STANDBY, ACTIVE, MCU ONLY, Suspend-to-RAM MCU ONLY
20 NSLEEP1 goes low and NSLEEP2 goes high(5) False False ACTIVE, MCU ONLY, Suspend-to-RAM MCU ONLY
21 NSLEEP1 goes low and NSLEEP2 goes low(5) False False ACTIVE, MCU ONLY Suspend-to-RAM TO_S2R
22 NSLEEP1 goes high and NSLEEP2 goes low(5) False False ACTIVE, MCU ONLY Suspend-to-RAM
23 I2C_0 bit goes high(3) False False STANDBY, ACTIVE, MCU ONLY STANDBY TO_STANDBY
24 I2C_3 bit goes high(3) False False ACTIVE, MCU ONLY No State Change Devices are prepared for OTA NVM update.(6)
(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see RECOV_CNT_REG_2, in Table 5-10). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a power cycle. Refer to the datasheet for more details.
(2) If the LP_STANDBY_SEL bit is set, then the PFSM transitions to the hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the device as determined by the means of entering LP_STANDBY. Refer to the datasheet for more details.
(3) I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.
(4) Enabling the I2C CRC, enables the CRC on both I2C1 and I2C2, however, the I2C2 is disabled for 2ms after the CRC is enabled. Care should be taken when using the watchdog Q&A before enabling I2C CRC. The recommendation is to enable the I2C CRC first, and then after 2ms, start the watchdog Q&A.
(5) NSLEEP1 and NSLEEP2 of the primary PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.
(6) After completion of an OTA update, a reset of the PMICs is required to apply the new NVM settings.
(7) Trigger IDs 3, 25, and 26 are not described. These triggers are helper functions and transparent to the application.
(8) The PWR_SOC_ERR sequence results in the same regulator configuration as the TO_MCU sequence. However, in the event of an SOC power error the triggers to execute the TO_ACTIVE and TO_S2R sequences are masked. The processor must trigger the TO_MCU using trigger 20, as well as clearing relevant interrupts, before attempting to return to the ACTIVE state.