In this PDN, the PMIC devices have the
following four configured power states:
Standby
Active
MCU Only
Pwr SoC Error
DDR Retention
In Figure 6-1, the configured PDN power states are shown, along with the transition conditions to move
between the states. Additionally, the transitions to hardware states, such as SAFE RECOVERY
and LP_STANDBY are shown. The hardware states are part of the fixed device power Finite
State Machine (FSM) and described in the TPS6594-Q1 data sheet, see Section 8.
Figure 6-1 Pre-Configurable Finite State
Machine (PFSM) Mission States and Transitions
When the PMICs transition from the FSM to the
PFSM, several initialization instructions are performed to disable the residual voltage
checks on both the BUCK and LDO regulators, set the FIRST_STARTUP_DONE bit and clear the
VCCA OV and UV masks which are set in the static configurations, Table 5-8. After these instructions are executed the PMICs wait for a valid ON Request before
entering the ACTIVE state. The definition for each power state is described below:
STANDBYThe PMICs are powered by a valid supply on the system power rail (VCCA >
VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV
is forced low in this state. The processor is in the Off state, no voltage
domains are energized. Refer to the Section 6.3.2 sequence description.The STANDBY state is also entered when an error occurs and the PMIC transitions out of
the PFSM mission states and into the FSM states. When the device returns from the FSM
state the to PFSM the first state is represented by STANDBY with all of the resources
powered down and EN_DRV forced low. The sequence Section 6.3.1 is performed before the PMIC leaves the PFSM and enters the FSM state
SAFE_RECOVERY.
ACTIVEThe PMICs are powered by a valid supply. The PMICs are fully functional and
supply power to all PDN loads. The processor has completed a recommended
power up sequence with all voltage domains energized in both MCU and Main
processor sections. Refer to the Section 6.3.8 sequence description.
MCU_ONLYThe PMICs are powered by a valid supply. Only the power resources assigned to the MCU Safety
Island are on. Refer to the Section 6.3.7 sequence description.
Pwr SoC ErrorThe PMICs are powered by a valid supply. Only the power resources assigned to the MCU
Safety Island are on. Refer to the Section 6.3.5 sequence description. The only active trigger is 'B', requiring the PMICs to return
to the MCU_ONLY mode. The return to MCU_ONLY mode and eventually ACTIVE mode is only
recommended after the interrupts which caused the SOC_PWR_ERROR have been cleared.
RetentionThe PMICs are powered by a valid supply. When the PMICs I2C_7 triggers are set (DDR Retention),
only 3 SoC voltage domains (vdds_ddr_bias, vdds_ddr, and vdds_ddr_c) remain energized
while all other domains are off to minimize total system power. EN_DRV is forced low in
this state. Refer to the Section 6.3.9 sequence description.