SLVUCF3 March   2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , LP8764-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

7.2.2 RETENTION

As shown in Section 6.3.6, the MCU is powered off and therefore the transition out of the RETENTION to the MCU ONLY or the ACTIVE states must be configured before entering RETENTION. Similar to the MCU ONLY state the I2C_7 triggers must be set for both PMICs. Additionally, the LP876411B4 GPIO2 ( H_DDR_RET_1V1), must be set before entering RETENTION. In this example GPIO4 on the TPS65941213 is used to wake the device from RETENTION to ACTIVE.


Write 0x48:0x85:0x80:0x7F  // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0x34:0xC0;0x3F  // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7  // clear interrupt of gpio4, write to clear
Write 0x48:0x4F:0x00:0xF7  // unmask interrupt for GPIO4 falling edge
Write 0x4C:0x3D:0x02:0xFD  // set PMICB:GPIO2, H_DDR_RET_1V1
Write 0x48:0x86:0x00:0xFC  // trigger the TO_RETENTION power sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC  // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7  // clear interrupt of gpio4
Write 0x4C:0x3D:0x00:0xFD  // clear PMICB:GPIO2, DDR_RET

In this example the TPS65941213 RTC Timer is used to wake the device from RETENTION to ACTIVE.


Write 0x48:0x85:0x80:0x7F  // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0xC3:0x01;0xFE  // Enable Crystal
Write 0x48:0xC5:0x05:0xF8  // minute timer, enable TIMER interrupts
Write 0x48:0xC2:0x01:0xFE  // start timer, if the timer values are non-zero clear before starting
Write 0x4C:0x3D:0x02:0xFD  // set PMICB:GPIO2, H_DDR_RET_1V1
Write 0x48:0x86:0x00:0xFC  // trigger the TO_RETENTION power sequence
After the RTC Timer interrupt has occurred and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC  // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB  // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF  // clear timer interrupt, clear bit 5
Write 0x4C:0x3D:0x00:0xFD  // clear PMICB:GPIO2, DDR_RET