SLVUCF3 March   2022 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , LP8764-Q1 , TDA4VM , TDA4VM-Q1 , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 TO_ACTIVE
      6. 6.3.6 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Initialization
    2. 7.2 Moving Between States; ACTIVE and RETENTION
      1. 7.2.1 ACTIVE
      2. 7.2.2 RETENTION
    3. 7.3 Entering and Exiting Standby
    4. 7.4 Entering and Existing LP_STANDBY
    5. 7.5 Runtime Customization
  9. 8References

3.2 Control Mapping

Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the two PMIC devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication channel. This SPMI channel allows the TPS6594-Q1 and LP8764-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. With the SPMI the connection between the ENABLE pin or the LDO_VINT to the ENABLE pin (GPIO4) of the LP8764-Q1 is not required.

Other digital connections from the PMICs to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

The digital connections shown in Figure 3-2 allow system features including DDR Retention mode, functional safety up to ASIL-D, and compliant dual voltage SD card operation.

Figure 3-2 TPS6594-Q1 Digital Connections
  1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the device datasheet for a complete description. The PMIC voltage domains indicated are for the PDN-1A NVM configuration.
  2. PMIC_Wake1 is typically a CAN PHY INH output.
  3. LP_WKUP1 and WKUP1 transition to the ACTIVE state. Table 6-1
Note: The PMIC voltage domain of an IO can be different depending upon configuration. When configured as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and GPIO4 are in the VINT domain.
Note: In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2 Open-drain signals and Power Rail
PDN SignalPullup Power Rail
H_MCU_INTnVDD_IO_3V3
H_MCU_PORz_1V8VDA_LN_1V8
H_SOC_PORz_1V8VDA_LN_1V8
H_DDR_RET_1V1VDD_DDR_1V1_REG
H_WKUP_I2C0VDD_IO_3V3
H_MCU_I2C0_SCL/SDAVDD_IO_3V3

Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions.Reconfiguration is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). For details on how functional safety related connections help achieve functional safety system-level goals, see Section 4.

Table 3-3 Digital Connections by System Feature
Device GPIO Mapping System Features(1)
PMIC Pin NVM Function PDN Signals Active SoC Functional Safety DDR Retention SD Card USB Interface
TPS65941213-Q1 nPWRON/ ENABLE Enable SOC_PWR_ON R
nINT INT H_MCU_INTn R
nRSTOUT nRSTOUT H_MCU_PORz_1V8 R
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R
SDA_I2C1 SDA_I2C1 H_WKUP_I2C0 R
GPIO_1 SCL_I2C2 H_MCU_I2C0_SCL R
GPIO_2 SDA_I2C2 H_MCU_I2C0_SDA R
GPIO_3 nERR_SoC H_SOC_SAFETY_ERRn R
GPIO_4 LP_WKUP1(2) PMIC_WAKE1 R
GPIO_5 SCLK_SPMI LEOA_SCLK R
GPIO_6 SDATA_SPMI LEOA_SDATA R
GPIO_7 nERR_MCU H_MCU_SAFETY_ERRn R
GPIO_8 DISABLE_WDOG PMICA_GPIO8 R(3)
GPIO_9 GPO Unused(4) O
GPIO_10 WKUP1 H_PMIC_PWR_EN1 R
GPIO_11 nRSTOUT_SOC H_SOC_PORz_1V8 R
LP876411B4-Q1 nINT INT H_MCU_INTn R
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R
SDA_I2C1 SCL_I2C1 H_WKUP_I2C0 R
GPIO_1 GPO EN_VDDR R R
GPIO_2 GPO H_DDR_RET_1V1 R
GPIO_3 GPI Unused(4) O
GPIO_4(5) ENABLE PMICB_GPIO4 O
GPIO_5 GPI Unused(4) O
GPIO_6 GPI Unused(4) O
GPIO_7 GPI Unused(4) O
GPIO_8 SCLK_SPMI LEOA_SCLK R
GPIO_9 SDATA_SPMI LEOA_SDATA R
GPIO_10 GPO EN_3V3IO_LDSW R R R R
(1) R is Required. O is optional.
(2) LP_WKUP1 function is masked in the static settings. Instructions for unmasking the function are provided in Section 7.2.2, Section 7.3 and Section 7.4.
(3) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(4) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if desired.
(5) GPIO4 of the LP876411B4-Q1 is not required for the PDN-1A to function correctly.