SLVUCI2 march   2023 AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TPS6594-Q1

 

  1.   TPS6594133A-Q1 PMIC User Guide for Jacinto J784S4 or J721S2, PDN-3A, PDN-3B, PDN-3F
  2.   Trademarks
  3. 1Introduction
  4. 2Processor Connections
    1. 2.1 Power Mapping
    2. 2.2 Control Mapping
  5. 3Supporting Functional Safety Systems
    1. 3.1 Achieving ASIL-B System Requirements
    2. 3.2 Achieving up to ASIL-D System Requirements
  6. 4Static NVM Settings.
    1. 4.1  Application-Based Configuration Settings
    2. 4.2  Device Identification Settings
    3. 4.3  BUCK Settings
    4. 4.4  LDO Settings
    5. 4.5  VCCA Settings
    6. 4.6  GPIO Settings
    7. 4.7  Finite State Machine (FSM) Settings
    8. 4.8  Interrupt Settings
    9. 4.9  POWERGOOD Settings
    10. 4.10 Miscellaneous Settings
    11. 4.11 Interface Settings
    12. 4.12 Multi-Device Settings
    13. 4.13 Watchdog Settings
  7. 5Pre-Configurable Finite State Machine (PFSM) Settings
    1. 5.1 Configured States
    2. 5.2 PFSM Triggers
    3. 5.3 Power Sequences
      1. 5.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 5.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 5.3.3 ACTIVE_TO_WARM
      4. 5.3.4 ESM_SOC_ERROR
      5. 5.3.5 PWR_SOC_ERROR
      6. 5.3.6 MCU_TO_WARM
      7. 5.3.7 TO_MCU
      8. 5.3.8 TO_ACTIVE
      9. 5.3.9 TO_RETENTION
  8. 6Application Examples
    1. 6.1 Initialization
    2. 6.2 Moving Between States; ACTIVE, MCU ONLY and RETENTION
      1. 6.2.1 ACTIVE
      2. 6.2.2 MCU ONLY
      3. 6.2.3 RETENTION
    3. 6.3 Entering and Exiting Standby
    4. 6.4 Entering and Existing LP_STANDBY
  9. 7References

5.3.2 TO_SAFE_ORDERLY and TO_STANDBY

If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs using the recommended power down sequence and proceed to the SAFE state.

If an OFF request occurs, such as the ENABLE pin of the TPS6594133A device being pulled low, the same power down sequence occurs, except that the PMIC goes to STANDBY (LP_STANDBY_SEL=0) or LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the SAFE state. The power sequence for both of these events is shown in .

GUID-0FE17603-EA2D-4488-87C3-6FEC6CA90ABA-low.svgFigure 5-3 TO_SAFE_ORDERLY and TO_STANDBY Power Sequence

At the end of the TO_SAFE_ORDERLY the PMIC wait approximately 16 ms before executing the following instructions:

 //TPS6594133A 
// Set LPM_EN 
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xEB
// Reset all BUCKs 
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0
The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY state. SAFE_RECOVERY means that the PMIC leaves the mission state. The SAFE_RECOVERY state is where the recovery mechanism increments the recovery counter and determines if the recovery count threshold (see Table 4-10) is reached before attempting to recover.

At the end of the TO_STANDBY sequence, the same AMUXOUT_EN, CLKMON_EN, and LPM_EN bit manipulations are made in the PMIC. The BUCKs are not reset. After these instructions, the PMIC performs an additional check to determine if the LP_STANDBY_SEL (see Table 4-10) is true. If true then the PMICs enter the LP_STANDBY state and leave the mission state. If the LP_STANDBY_SEL is false, then the PMICs remain in the mission state defined by STANDBY in Configured States.