The PDN-3x base power resources are the TPS6594133A-Q1 PMIC, two High-Current Power Stages (HCPS-A & HCPS-B), two TPS389006004-Q1 Safety Voltage Supervisors, two TPS74501P-Q1 LDOs and one TPS622965-Q1 load switch. The processor CPU and CORE power rails are powered by HCPS-A and HCPS-B respectively. Each HCPS consists of one or multiple, stackable TPS6287xY1-Q1 buck converters. Please refer toTable 2-1 for recommended HCPS configurations based upon JS84S4 or J721S2 processor type. The PMIC has built-in input supply voltage level detection which enables it to use either a 3.3V or 5V system input voltage. If a system does use a 5V input, then the load switches used to supply the processor with 3.3V for IO signaling need to be replaced with either a buck converter or LDO depending upon overall system needs.

For Functional Safety applications, the PMIC provides majority of all key requirements, see TPS6594 Data Sheet for more details. In addition, there is a protection FET before VCCA that connects to the OVPGDRV pin of the PMIC, allowing voltage monitoring of the input supply. Two TPS389006004-Q1 Safety Voltage Supervisors (SVS) are used for OV/UV monitoring on all discrete power resource voltages as required for functional safety systems that are ASIL-B/D capable.

Figure 2-1 shows PDN-3A power map for supplying a J784S4 or J721S2 processor platform (SoC, Flaxh & LPDDR4 memories, power resources) with base features plus all optional features that includes three processor low power modes (MCU Only, GPIO Retention and DDR Retention) and three optional functions (UHS-I SD card, USB2.0 interface and HS eFuse programming). Figure 2-2 depicts PDN-3F power map using only the PDN-3x base power resources to support the base feature set (ASIL-D safety capable system, MCU & Main supply isolation, MCU Safety Island, MCU Only low power mode, dual voltage 1.8/3.3V IO signaling, four LPDDR4 memories, OSPI boot Flash & eMMC storage Flash).

Figure 2-1 PDN-3A Power Connections - Full Features

Figure 2-2 PDN-3F Power Connections - Reduced Features

Table 2-2 identifies the required power resources and rails needed to support PDN-3A full featured system. If a feature is not desired, the power resource and rail may be removed but the processor input supply must be connected to another power rail of like voltage & type since all supplies need to be energized for full active operations. Table XYZ gives guidance on grouping of processor input supplies into base power rails if any of the three low power modes or optional functions are not desired. Applying this guidance to the full featured PDN-3A scheme enables other PDN-3x variants (x = B/C/D/E/ F) that support end products with different feature sets in between PDN-3A and PDN-3F.