SLWU086C November   2013  – January 2016 ADS42JB46 , ADS42JB49 , ADS42JB69 , DAC38J84

 

  1.   TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator Card User's Guide
    1.     Trademarks
    2. 1 Functionality
      1. 1.1 ADC EVM Data Capture
      2. 1.2 DAC EVM Pattern Generator
    3. 2 Hardware Configuration
      1. 2.1 Power Connections
      2. 2.2 Switches, Jumpers, and LEDs
        1. 2.2.1 Switches and Pushbuttons
        2. 2.2.2 Jumpers
      3. 2.3 LEDs
        1. 2.3.1 Power and Configuration LEDs
        2. 2.3.2 Status LEDs
        3. 2.3.3 Connectors
          1. 2.3.3.1 SMA Connectors
          2. 2.3.3.2 FPGA Mezzanine Card (FMC) Connector
          3. 2.3.3.3 JTAG Connectors
          4. 2.3.3.4 USB I/O Connection
    4. 3 Software Start-Up
      1. 3.1 Installation Instructions
      2. 3.2 USB Interface and Drivers
    5. 4 Downloading Firmware
  2.   Revision History

1.1 ADC EVM Data Capture

New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard. These devices are generally available on an EVM that connects directly to the TSW14J56EVM. The common connector between the EVMs and the TSW14J56EVM is a Samtec high-speed, high-density FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A common pinout for the connector across a family of EVMs has been established. At present, the interface between the EVMs and the TSW14J56EVM has defined connections for 10 lanes of serial differential data, two device clock pairs, two JESD204B SYSREF and SYNC pairs. There are four over-range single-ended indicators, 12 spare general purpose CMOS I/O pins, and 29 spare differential LVDS or 58 single-ended CMOS signals. The board has a spare SMA interface to the FPGA, 4 spare dip switches, a pushbutton switch, several spare test points routed to the FPGA and 8 status LED's.

The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B spec can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the TSW14J56 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from 1 to 8.

The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on the ADC device selected in the device drop down window. Each ADC device that appears in this window has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of lanes, number of converters, octets per frame, and other parameters. This information is loaded into the FPGA registers after the user clicks on the capture button. After the parameters are loaded, synchronization is established between the data converter and FPGA and valid data is then captured into the on-board memory. See the High-Speed Data Capture Pro GUI Software User's Guide SLWU087 and section 2.3 in the guide for more information. Several .ini files are available to allow the user to load pre-determined ADC JESD204B interfaces. For example, if the user selects the ADC called "ADS42JB69_LMF_421", the FPGA will be configured to capture data from the ADS42JB69EVM with the ADC JESD interface configured for 4 lanes, 2 converters, and 1 octet per frame.

The TSW14J56 device can capture up to 2G 16-bit samples at a maximum line rate of 12.5 Gbps that are stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data from memory and transmits parallel data to the on-board high-speed parallel-to-USB converter.