Key limiting factor No. 3: turn-on and turn-off losses

Parasitic loop inductances can cause a number of switching-related losses, which can significantly reduce efficiency. Consider again a buck converter with the high-side MOSFET conducting the inductor current. Turning the high-side switch off interrupts the current through the parasitic inductance. The transient currents (di/dt), along with the parasitic loop inductance, induce a voltage spike. The higher the di/dt, the lower the switching losses, with the consequence of higher device voltage stress. At some turn-off speeds, the buck converter highside switch suffers from breakdown. Thus, you must carefully control the switching speeds in order to maximize efficiency while keeping the DC/DC converter operating in its safe operating area. For more information, see the application note Understanding SOA Curves to Operate at High Output Currents and Temperature.

Additionally, reducing the drain charge of the highside MOSFET can also lead to additional voltage spikes on it, given that there is less capacitance as part of the inductor-capacitor network to absorb the energy stored in the parasitic loop inductance. This presents an additional challenge, as it’s best to keep the drain charge as low as possible to reduce the previously mentioned charge-related losses. Mitigating the overall losses associated with these parasitics typically requires that you reduce the loop inductance itself, along with employing other gate-driver techniques.