SLYY193C january   2023  – april 2023 LMQ61460-Q1 , TPS54319 , TPS62088 , TPS82671 , UCC12040 , UCC12050

 

  1.   At a glance
  2.   Authors
  3.   3
  4.   What is power density?
  5.   What limits power density?
  6.   What limits power density: switching losses
  7.   Key limiting factor No. 1: charge-related losses
  8.   Key limiting factor No. 2: reverse-recovery losses
  9.   Key limiting factor No. 3: turn-on and turn-off losses
  10.   What limits power density: thermal performance
  11.   How to break through power density barriers
  12.   Switching loss innovations
  13.   Package thermal innovations
  14.   Advanced circuit design innovations
  15.   Integration innovations
  16.   Conclusion
  17.   Additional resources

Key limiting factor No. 1: charge-related losses

In any hard-switched DC/DC converter, charging and discharging parasitic capacitances in the system requires some amount of energy. For a given switch technology and voltage rating, Equation 2 and Equation 3 estimate these losses as:

Equation 2. P S W = 1 2 × C D S × V D S 2 × f S W
Equation 3. P G A T E = Q G × V G × f S W

where

  • CDS is the MOSFET drain-to-source capacitance
  • VDS is the MOSFET drain-to-source voltage
  • fSW is the switching frequency
  • QG is the gate charge
  • VG is the gate-to-source voltage

As you can see from Equation 2 and Equation 3, you can reduce these losses primarily by reducing the switching frequency (not desirable), improving the MOSFET charge-related FoMs (QG and CDS) or trading off conduction losses with switching losses.