TI power process technologies feature optimized low-power design components. High-density resistors and capacitors combined with novel circuit techniques enable a reduction in both I_Q and die area. Power FETs and digital logic provide low-leakage transistors while simultaneously being optimized for speed; thus, I_SHDN and area are not exclusively compromised. Additionally, accurate modeling of subthreshold operation at lower V_GS-V_T levels – as shown in Figure 18 – enables reliable operation down to the picoampere/micrometer biasing level.

Figure 18 Sigma IDS percentage mismatch vs. V_GS – V_T .