SLYY222A November   2023  – November 2024 ADC12DJ5200RF , ADS127L11 , BQ79731-Q1 , REF35 , REF70 , TPS62912 , TPS62913 , TPS7A20 , TPS7A94 , TPSM82912 , TPSM82913

 

  1.   1
  2.   Overview
  3.   At a glance
  4.   Noise and ADCs
  5.   Defining noise and precision in a power architecture
  6.   Innovations in low-noise and low-power voltage references
  7.   Innovations in buried Zener voltage references
  8.   Innovations in ultra-low-noise voltage references
  9.   Improving noise and thermal performance with simplified power architectures
  10.   High-current low noise with LDO supply rails
  11.   Innovations in precision battery monitoring
  12.   Conclusion
  13.   Additional resources
Reducing inherent and system noise is critical to enabling high-precision signal chains in demanding electronic systems. Innovations in low-noise power devices are helping to mitigate system noise and improve accuracy and precision.

Achieving the lowest noise in a signal chain is vital as industry trends push the boundaries of resolution and precision. And when pushing these boundaries, it’s important to consider not just the noise of signal-chain components such as analog-to-digital converters (ADCs) and amplifiers, but also power products such as switching and low-dropout regulators (LDOs). Advances in silicon technologies have reduced the trade-offs when attempting to achieve low noise and high precision in power topologies.

Recent trends in 24-bit delta-sigma ADCs have increased sampling speeds and lowered power consumption. New low-noise power supplies and low-noise voltage references can take advantage of these trends and help ADCs achieve high-resolution measurements in low-power applications.

To achieve the lowest noise, let’s review the sources of noise in the signal chain and power architecture. Figure 1 shows a typical signal-chain application centered around an ADC that requires an external voltage reference, clock and signal-conditioning circuit. Every component in Figure 1 contributes to system noise and requires optimization.

 Common signal-chain power
                    architecture. Figure 1 Common signal-chain power architecture.

Marcoo Zamora

System Engineer

Linear Power