SLYY222A November   2023  – November 2024 ADC12DJ5200RF , ADS127L11 , BQ79731-Q1 , REF35 , REF70 , TPS62912 , TPS62913 , TPS7A20 , TPS7A94 , TPSM82912 , TPSM82913

 

  1.   1
  2.   Overview
  3.   At a glance
  4.   Noise and ADCs
  5.   Defining noise and precision in a power architecture
  6.   Innovations in low-noise and low-power voltage references
  7.   Innovations in buried Zener voltage references
  8.   Innovations in ultra-low-noise voltage references
  9.   Improving noise and thermal performance with simplified power architectures
  10.   High-current low noise with LDO supply rails
  11.   Innovations in precision battery monitoring
  12.   Conclusion
  13.   Additional resources

Improving noise and thermal performance with simplified power architectures

The traditional setup for powering a clock, data converter or amplifier is to use a DC/DC converter (or module), followed by an LDO, followed by a ferrite-bead filter, as shown in Figure 13. This design approach minimizes both noise and ripple from the power supply and works well for load currents below approximately 2 A. As loads increase, however, power losses in the LDO introduce issues in efficiency and thermal management; for example, a post-regulation LDO can add 1.5 W of power loss in a typical analog front-end application.

A typical low-noise architecture using a DC/DC converter, LDO and ferrite-bead filter. Figure 13 A typical low-noise architecture using a DC/DC converter, LDO and ferrite-bead filter.

The benefits of an LDO in a typical power architecture are to provide an accurate voltage rail while lowering switching noise in the high-frequency noise region with a high PSRR. The trade-off of using an LDO is an increase in thermals and power consumption. An effective way to ensure low noise while controlling power losses is to eliminate the LDO from the design altogether and use a low-noise DC/DC buck converter or module, as shown in Figure 14. This LDO-less design lowers power losses and improves thermals while achieving low noise.

Using a low-noise buck converter without an LDO. Figure 14 Using a low-noise buck converter without an LDO.

The TPS62912 and TPS62913 family of low-noise buck converters, as well as the TPSM82912 and TPSM82913 modules, implement a noise-reduction/soft-start pin for connecting a capacitor, forming a low-pass resistor-capacitor filter using the integrated Rf and externally connected CNR/SS, as shown in Figure 15. This implementation essentially mimics the behavior of the band-gap low-pass filter in an LDO, which allows for an output-voltage ripple below 10 μVRMS. The TPS62913 can also achieve a low noise floor in the high-frequency region that is absent of the typical switching noise by taking advantage of the 2.2-MHz switching frequency and optional second-stage ferrite-bead inductor-capacitor filter.

Low-noise buck converter block diagram with band-gap noise filtering. Figure 15 Low-noise buck converter block diagram with band-gap noise filtering.

The ADC12DJ5200RF is an RF-sampling ADC that samples from DC to 10 GHz with 4 W of power consumption. The PSRR attenuates any power-supply ripple and noise, but any residual ripple and noise will appear on the ADC output spectrum, which causes an error. The ADC12DJ5200RF has more sensitive power-supply requirements on the analog voltage rails, and therefore requires low noise. Using the TPS62912 for low-noise and high-power analog rails enables a simplified and efficient power architecture, while minimizing power losses compared to a DC/DC-plus-LDO combination.