SNAA386 November 2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
In Common Clock (CC) architectures, both the transmitter and receiver devices are clocked by the same PLL. Figure 3-1 shows a block diagram of this architecture. Common clock is the most widely supported PCIe clocking architecture. This architecture easily supports SSC on both PCIe devices for EMI reduction, allowing for Common Clock with Spread (CCS). Figure 3-1 shows a typical common clock architecture.