Figure 3-4 shows the setup of a typical Common Clock architecture with the path for data transfer. The transmitter is composed of the TX PLL and the TX Latch, and the receiver is composed of the RX PLL, RX Clock Data Recovery (CDR), and the RX Latch. REFCLK is provided to both the transmitter and the receiver, but the jitter at the receiver is impacted by the PLLs of both PCIe devices, the CDR of the receiver, and the delay between the transmission of the REFCLK through the two paths to the RX latch.

Equation 5 shows the overall transfer function of the affect of REFCLK at RX Latch. The values for the damping factors ζ and frequencies f are set by the PCIe standard based on the generation. The PLLs of TX and RX function as second order low-pass filters. Up to PCIe Gen 4.0, the CDR behaves as a first order high-pass filter. For PCIe Gen 5.0 and PCIe Gen 6.0, the CDR behaves as a second-order high-pass filter.

For PCIe Gen 5.0 and PCIe Gen 6.0, the CDR is defined differently. For these generations, the CDR is represented by a second-order high-pass filter. Equation 6 is the equation for this filter.

For PCIe Gen 5.0, ω₀ = 20 × 10⁶ × 2π, ω₁ =1.1 × 10⁶ × 2π, ω_LF = 160 × 10³ × 2π

For PCIe Gen 6.0, ω₀ = 10 × 10⁶ × 2π, ω₁ =3.88 × 10⁶ × 2π, ω_LF = 87 × 10³ × 2π

Figure 3-5 is a visual representation of the bandwidth of the system for PCIe Gen 6.0. Table 3-2 provides the PCIe jitter filter characteristics for Gen 6.0. There are 16 possible jitter filter combinations. The PCIe standard lists the full jitter filter characteristics for each generation. The values for ω and ζ vary from generation to generation.